NDLI: Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM

Content Provider	IEEE Xplore Digital Library
Author	Minjie Lv Hongbin Sun Qiwei Ren Bing Yu Jingmin Xin Nanning Zheng
Copyright Year	2004
Abstract	Three-dimensional (3D) integration is promising to provide dramatic performance and energy efficiency improvement to 3D logic-DRAM integrated computing system, but also poses significant challenge to the yield. To address this challenge, this paper explores a way to leverage logic-DRAM co-design to reactivate unused spares and thereby enable the cost-efficient technique to repair 3D integration-induced defective DRAM cells after die stacking. In particular, we propose to make the DRAM array open its spares to off-chip access by a small architectural modification and further design the defective address comparison and redundant address remapping with an efficient architecture on logic die to achieve equivalent memory repair. Simulation results demonstrate that the proposed repair technique for stacked DRAM can significantly alleviate potential yield loss, with minimal area and power consumption overhead and negligible timing penalty.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1362
Ending Page	1371
Page Count	10
File Size	1496103
File Format	PDF
ISSN	15498328
Volume Number	62
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Maintenance engineering Redundancy Arrays Fuses Three-dimensional displays Stacking yield Memory repair redundancy 3D DRAM 3D integration
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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