NDLI: A Novel Quasi-3-D Interface-Trapped-Charge-Induced Threshold Voltage Model for Quadruple-Gate MOSFETs, Including Equivalent Number of Gates

Content Provider	IEEE Xplore Digital Library
Author	Chiang Te-Kuang
Copyright Year	1963
Abstract	With the effects of interface trapped charges on the flat-band voltage, we report a novel quasi-3-D interface-trapped-charge-induced threshold voltage model for quadruple-gate (QG) MOSFETs based on the scaling equation including equivalent number of gates. It is found that a thin gate oxide and a small ratio of damaged region to channel region are required to reduce the threshold voltage degradation by the trapped charges. In addition, the damaged device with a thick silicon film suffers the small threshold voltage degradation by the negative trapped charges. In comparison with other multiple-gate MOSFETs, the QG MOSFET is better than double-gate and triple-gate MOSFETs in suppressing the threshold voltage degradation by the positive trapped charges. The model can be used to explore the hot-carrier-induced threshold voltage of the QG MOSFET for its memory device application.
Sponsorship	IEEE Electron Devices Society
Starting Page	1615
Ending Page	1618
Page Count	4
File Size	973665
File Format	PDF
ISSN	00189383
Volume Number	61
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage MOSFET Logic gates Semiconductor device modeling Silicon Mathematical model quadruple-gate (QG) MOSFETs. Bulk scaling equation equivalent number of gates (ENG) interface-trapped-charge-induced threshold voltage quadruple-gate (QG) MOSFETs
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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