NDLI: Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS

Content Provider	IEEE Xplore Digital Library
Author	Tajalli, A. Leblebici, Y.
Copyright Year	2004
Abstract	While the general trend in CMOS technology scaling is mostly focused on high-performance and high-speed circuits, the potential use of advanced nanoscale technologies for ultra-low power (ULP) applications with lower operating frequencies is still debated. In these types of applications, the supply voltage is generally reduced well below threshold voltage of MOS devices in order to limit dissipation and to control the device leakage current due to the subthreshold channel residual current. However, recent studies show that reducing the supply voltage increases the device susceptibility to process variations, resulting in delay spread and decreased noise margin. This article presents an analytical approach for studying the effect of technology scaling and variability on performance of ULP integrated systems. Unlike the conventional design methodologies, we include the effect of process variation on circuit performance (such as on noise margin and delay) in each step of design and optimization. Here, the power dissipation and noise margin are both calculated as a function of turn-on and turn-off current of devices. This approach helps to explore the effect of these two quantities on performance of CMOS digital circuits. The trade-offs between the choice of supply voltage, threshold voltage, device dimensions, delay performance, activity rate, and power consumption are analytically examined using predictive device models, for different technology nodes. Taking into account the circuit reliability requirements, this analysis can be used to optimize the system performance with proper device sizing and selecting supply voltage.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2189
Ending Page	2200
Page Count	12
File Size	1234679
File Format	PDF
ISSN	15498328
Volume Number	58
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise CMOS integrated circuits Logic gates Threshold voltage MOS devices Transistors Inverters weak inversion CMOS logic digital CMOS circuits energy consumption noise margin power-delay product subthreshold ultra low power
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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