NDLI: Switching Loss Analysis Considering Parasitic Loop Inductance With Current Source Drivers for Buck Converters

Content Provider	IEEE Xplore Digital Library
Author	Zhiliang Zhang Jizhen Fu Yan-Fei Liu Sen, P.C.
Copyright Year	1986
Abstract	In this letter, the switching loop inductance was investigated on the current-source drivers (CSDs). The analytical model was developed to predict the switching losses. It is noted that although the CSDs can greatly reduce the switching transition time and switching loss, the switching loop inductance still causes the current holding effect on the CSDs. This results in high turn-off loss for the control MOSFET in a buck converter. An improved layout was proposed to achieve minimum switching loop inductance. The experimental results verified the significant switching loss reduction owing to the proposed layout of a 1-MHz buck converter with 12-V input, and 1.3-V and 30-A output.
Sponsorship	IEEE Power Electronics Society
Starting Page	1815
Ending Page	1819
Page Count	5
File Size	655714
File Format	PDF
ISSN	08858993
Volume Number	26
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inductance Switches Switching loss Driver circuits MOSFET circuits Analytical models Logic gates voltage regulator module (VRM) Buck converter current-source driver (CSD) power MOSFET resonant gate driver voltage regulator (VR)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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