NDLI: Simultaneous Layout Migration and Decomposition for Double Patterning Technology

Content Provider	IEEE Xplore Digital Library
Author	Chin-Hsiung Hsu Yao-Wen Chang Nassif, S.R.
Copyright Year	1982
Abstract	Double patterning technology (DPT) and layout migration (LM) are two closely related problems on design for manufacturability in the nanometer era. DPT decomposes a layout into two masks and applies double exposure patterning to increase pitch size and, thus, printability. In this paper, we present the first algorithm in the literature for the simultaneous layout migration and decomposition (SMD) problem. Our algorithm first constructs a potential conflict graph and DPT-aware constraint graphs, and then applies integer linear programming (ILP) corresponding to the graphs to obtain a decomposed and migrated layout. We further present an effective graph-based reduction technique to prune the ILP solution space, which maintains the same DPT conflicts. We also present a new DPT-aware objective for the SMD problem to minimize the difference between the original and migrated layouts while considering the DPT effects. In addition, we present an approach to generate DPT-aware standard cells by considering the DPT effects on the cell boundaries; this technique improves the layout printability and facilitates electronic design automation tools to consider DPT. Experimental results show that our algorithms can effectively generate conflict-free migrated layouts with 11% smaller layout areas and 21% smaller layout changes, compared with the traditional method of layout decomposition followed by LM. In particular, our reduction technique reduces the ILP variables by 45.7%, the ILP constraints by 58.5%, and the DPT edges by 79.9% over the basic ILP formulation, leading to a substantial speedup. For example, it can reduce the runtimes for the test cases from more than one day to only seconds.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	284
Ending Page	294
Page Count	11
File Size	1809496
File Format	PDF
ISSN	02780070
Volume Number	30
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Layout Libraries Design automation System-on-a-chip Lithography physical design Constraint graph design for manufacturability double patterning integer linear programming (ILP) layout migration (LM)
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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