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Content Provider | IEEE Xplore Digital Library |
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Author | Younis, N. Ashour, M. Nassar, A. |
Copyright Year | 2004 |
Abstract | A power-efficient clock/data distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed with respect to the decimation factor. Both proposed and conventional comb filters are implemented using Xilinx Spartan3 low-power field-programmable gate array family. The implementation results show that applying the proposed technique reduces the dynamic power consumption of the second- and third-order polyphase comb filters up to 62.87% and 57.6%, respectively, depending on the decimation factor and the number of quantizer bits. For a particular power consumption, a higher input sampling rate can be utilized by applying the proposed technique. Consequently, the signal-to-noise ratio of a second-order SigmaDelta modulator is increased using second- and third-order modified filters by 21.6 and 20.5 dB, respectively, depending on the decimation factor and the number of quantizer bits. |
Sponsorship | IEEE Circuits and Systems Society |
Starting Page | 639 |
Ending Page | 643 |
Page Count | 5 |
File Size | 506618 |
File Format | |
ISSN | 15497747 |
Volume Number | 56 |
Issue Number | 8 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-08-01 |
Publisher Place | U.S.A. |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Clocks Digital filters Finite impulse response filter Energy consumption Sampling methods Delta-sigma modulation Digital modulation Signal processing Microelectronics Frequency $\Sigma\Delta$ modulator Comb filters polyphase decomposition power consumption |
Content Type | Text |
Resource Type | Article |
Subject | Electrical and Electronic Engineering |
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