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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Baeg, S. |
| Copyright Year | 2004 |
| Abstract | Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 times 72 TCAM is designed using 0.18-mum CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture. |
| Sponsorship | IEEE Circuits and Systems Society |
| Starting Page | 1485 |
| Ending Page | 1494 |
| Page Count | 10 |
| File Size | 694796 |
| File Format | |
| ISSN | 15498328 |
| Volume Number | 55 |
| Issue Number | 6 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-07-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Energy consumption Computer aided manufacturing CADCAM Circuits Random access memory Read-write memory Capacitors CMOS technology Delay effects Voltage memory architecture Content-addressable memory (CAM) low-power design match line Memory Architecture match-line Content Addressable Memory Low Power Design Match-Line |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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