NDLI: Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000

Content Provider	IEEE Xplore Digital Library
Author	Yi-Zhen Zhang Chao Xu Wen-Tao Wang Liang-Bin Chen
Copyright Year	1991
Abstract	The algorithm of embedded block coding with optimization truncation (EBCOT) is one of the key techniques in JPEG2000 standard. The high-speed/performance hardware designs for EBCOT are critical to various high-resolution applications, such as digital cameras, digital video recorders, and HDTV, etc. This paper presents a detailed performance analysis for EBCOT Tier-1 and its bit plane parallel architecture design. By analyzing the bit plane parallel context modeling, we conclude that the difference between the output rate of context modeling module and that of arithmetic coding module degrades the performance of whole EBCOT parallel encoding. We propose two improved methods, referred to as data-pairs ordering (DPO) and flexible MQ (FMQ) coder. It solves the configuration problem between the parallel context modeling module and the sequent arithmetic coding module, takes full advantage of the bit plane parallel encoding technique, and improves the coding speed and efficiency of the EBCOT encoder significantly. The design of parallel EBCOT encoder is tested on the field-programmable gate array (FPGA) platform of Altera Company. The simulation results show that it can on average encode 54 million samples at 55-MHz working frequency. It is equivalent to encoding a 90006000 image per second or encoding 720 p (1280times720, 4:2:2) HDTV picture sequence nearly 30 frames per second. Compared with the conventional bit plane parallel architecture design, the proposed one can reduce execution time by 24%.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1336
Ending Page	1347
Page Count	12
File Size	1395134
File Format	PDF
ISSN	10518215
Volume Number	17
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance analysis Context modeling HDTV Parallel architectures Arithmetic Encoding Field programmable gate arrays Image coding Block codes Hardware VLSI Embedded block coding with optimized truncation (EBCOT) JPEG2000 parallel architectures
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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