NDLI: A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000

Content Provider	IEEE Xplore Digital Library
Author	Yijun Li Bayoumi, M.
Copyright Year	1991
Abstract	For JPEG 2000-based multimedia systems, embedded block coding with optimized truncation (EBCOT) tier-1 has become a bottleneck for the entire system. EBCOT tier-1 is full with bit operation, so hardware implementation is more efficient in both system throughput and power consumption. In this paper, a three-level parallel high-speed power-efficient architecture for EBCOT tier-1 is proposed. This architecture is divided into bit-plane coding (BC), arithmetic encoding (AE), and first-in first-out (FIFO) that connects BC with AE and balances the different throughput between them. To improve the system throughput, three levels of parallelism in BC are adopted: 1) the parallelism among bit planes; 2) the parallelism among three pass scans; and 3) the parallelism among coding bits. AE is implemented in four pipeline stages. To achieve power efficiency, several techniques are applied: in BC, simple control logics are added to reduce computation in BC; in FIFO, memory access is reduced since AE is fed with fixed values instead of reading from FIFO; in AE, simple control logics are added to reduce computation in AE and forwarding technique combined with clock gating is adopted to reduce switching activities in the last two pipeline stages. The proposed architecture can encode one code block with size NtimesN in only around (0.35~0.46)timesNtimesN clock cycles. Experimental results, with standard test image benchmarks, show that the proposed power reduction techniques keep the same system throughput and achieve about 27% improvement in the power consumption by comparison with the architecture without these techniques
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1153
Ending Page	1163
Page Count	11
File Size	735282
File Format	PDF
ISSN	10518215
Volume Number	16
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput Parallel processing Energy consumption Pipelines Logic Clocks Multimedia systems Block codes Hardware Arithmetic VLSI architecture EBCOT tier-1 high-speed JPEG 2000 low-power memory-efficient
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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