NDLI: The study of hot-carrier stress on poly-Si TFT employing C-V measurement

Content Provider	IEEE Xplore Digital Library
Author	Kook Chul Moon Jae-Hoon Lee Min-Koo Han
Copyright Year	1963
Abstract	The degradation of n-type and p-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) due to hot-carrier stress was investigated by capacitance-voltage (C-V) measurement. In C-V measurements, the fixed charges in the gate oxide of TFTs are not affected by a small-applied signal, whereas the trap states in the bandgap respond to the applied frequency, so that the dominant degradation mechanism of poly-Si TFTs can be evaluated. The capacitance (C/sub GS/) between the source and the gate, as well as the capacitance (C/sub GD/) between the drain and the gate, were measured. The difference between the C/sub GD/ and the C/sub GS/ indicates the location of degradation in the TFT. Our experimental results showed that the degradation of n-type TFTs was caused by additional trap states in the grain boundary, whereas the degradation of p-type TFTs was caused by electron trapping into the gate oxide.
Sponsorship	IEEE Electron Devices Society
Starting Page	512
Ending Page	517
Page Count	6
File Size	423040
File Format	PDF
ISSN	00189383
Volume Number	52
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-04-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thin film transistors Hot carriers Capacitance measurement Voltage measurement Charge carrier lifetime Semiconductor device reliability Silicon thin-film transistor (TFTs) Capacitance–voltage (C–V) hot carrier poly-Si reliability
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Electronic, Optical and Magnetic Materials

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