NDLI: Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

Content Provider	IEEE Xplore Digital Library
Author	Schuster, S.E. Cook, P.W.
Copyright Year	1966
Abstract	Interlocked pipelined CMOS (IPCMOS), a new asynchronous set of clock circuits suitable for high-frequency and low-power operation, is described. In IPCMOS, the reduced power results from enabling the local clocks only when there is an operation to perform and from a simple single-stage latch. The single-stage latch can be used because the locally generated clocks driving adjacent stages are not enabled simultaneously. The combination of enabling the clocks only when there is an operation to perform and the simple latch can lower power by a factor of five to ten times in many applications. In IPCMOS, the staggered local clocks also result in a significant reduction of dynamic Ldi/dt noise. In addition to the locally generated interlocked clocks and the single-stage latch, unique circuits that combine the function of a static NOR and an input switch are key to achieving high performance and minimizing the overhead in the interlocking. In a 0.18-/spl mu/m bulk CMOS technology, these circuits drive a path through a typical 64-b multiplier stage at 3.3-4.5 GHz on an experimental chip. IPCMOS also provides a way to implement the interface between asynchronous and synchronous portions of a design, thereby giving the approach a great deal of flexibility by making it possible to drop IPCMOS into portions of an existing synchronous design.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	622
Ending Page	630
Page Count	9
File Size	482247
File Format	PDF
ISSN	00189200
Volume Number	38
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Latches Noise reduction Switches CMOS technology Frequency Circuit noise Switching circuits Digital circuits Power generation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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