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  1. IEEE Transactions on Device and Materials Reliability
  2. Year : 2001 Volume : 1
  3. Issue 4
  4. Effects of device design on InP-based HBT thermal resistance
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Year : 2015 Volume : 15
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Year : 2002 Volume : 2
Year : 2001 Volume : 1
Issue 4
Effect of a thin ionized-metal-plasma deposited Cu layer on the properties and thermal stability of Cu-TaN-SiO/sub 2/-Si structures
Analysis of erratic bits in flash memories
Effects of device design on InP-based HBT thermal resistance
Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices
Author index
Subject index
Issue 3
Issue 2
Issue 1

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Effects of device design on InP-based HBT thermal resistance

Content Provider IEEE Xplore Digital Library
Author Thomas III, S. Foschaar, J.A. Fields, C.H. Madhav, M.M. Sokolich, M. Rajavel, R.D. Binqiang Shi
Copyright Year 2001
Abstract The thermal resistance of InP-based single and double heterojunction bipolar transistors has been measured. The double heterojunction bipolar transistor (DHBT) device employs an InP collector to improve thermal conductivity and reduce the base-emitter junction temperature rise. DHBTs were grown with heavily doped InGaAs or InP sub-collectors for low resistance contacts. As expected, the all-InP collector (sub-collector and collector) had the lowest thermal resistance while the all-InGaAs collector (sub-collector and collector) had the highest thermal resistance. For a device with emitter size of 1 /spl times/ 3 /spl mu/m/sup 2/, the room temperature thermal resistance of the all-InP collector DHBT was 3.9/spl deg/C/mW. The DHBT with an InGaAs sub-collector had a thermal resistance of 5.6/spl deg/C/mW, while the SHBT had a thermal resistance of 12.3/spl deg/C/mW. Also compared were effects of device layout parameters on thermal resistance and the effect of the topside metal thickness. Devices with the largest perimeter-to-area ratio had the lowest thermal resistance when normalized to emitter area. HBTs with conservative alignment tolerances (L1) had similar thermal resistance to those with aggressive alignment tolerances (L2). The reduced parasitic capacitance of the L2-style SHBT improved the device f/sub T/ from 150 to 183 GHz at 6.0-mA collector current. Alternately, the reduced parasitics allowed the SHBT to operate at 150 GHz f/sub T/ at 2.9 mA, reducing the junction temperature rise by more than half. Doubling the topside metal thickness improved the thermal resistance by 31% at room temperature.
Sponsorship IEEE Electron Devices Society IEEE Reliability Society
Starting Page 185
Ending Page 189
Page Count 5
File Size 223647
File Format PDF
ISSN 15304388
Volume Number 1
Issue Number 4
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2001-12-01
Publisher Place U.S.A.
Access Restriction One Nation One Subscription (ONOS)
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Thermal resistance Heterojunction bipolar transistors Thermal conductivity Indium phosphide Temperature Indium gallium arsenide Double heterojunction bipolar transistors Electrical resistance measurement Dielectric substrates Resistance heating
Content Type Text
Resource Type Article
Subject Electronic, Optical and Magnetic Materials Safety, Risk, Reliability and Quality Electrical and Electronic Engineering
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