NDLI: Fast true delay estimation during high level synthesis

Content Provider	IEEE Xplore Digital Library
Author	Bhattacharya, S. Dey, S. Brglez, F.
Copyright Year	1982
Abstract	This paper addresses the problem of true delay estimation during high level design. The true delay is the delay of the longest sensitizable path in the resulting circuit, as opposed to the topological delay which is the delay of the longest path in the circuit. The existing delay estimation techniques either estimate the topological delay, which may be pessimistic if the longest path is unsensitizable or false, or estimate the true delay using gate-level timing analysis which may be prohibitively expensive. Resource sharing in high level synthesis can create false paths in the circuit implementation. Hence, determining the clock period using topological delay can be unduly conservative, resulting in excessive hardware to meet tight timing specifications. In this paper, we introduce an efficient technique to compute an estimate of the true delay. The proposed technique relies on partitioning the paths in the circuit and topological delay computation, and not on path sensitization. The paths in the implementation are partitioned into two sets given the high level information on scheduling and resource sharing: the complete determining path set (CDP/sub R/) and the nondetermining path set (NDP/sub R/). We prove that the delay of the longest path in CDP/sub R/ is lower bounded by the true delay and upper bounded by the topological delay of the circuit. Consequently, an estimate of the true delay of the resulting circuit can be computed by measuring the topological delay of the longest path in CDP/sub R/. We have developed a Functional delay ESTimation tool (FEST). Experimental results on a set of benchmarks reveal the following: approximately 50% of all paths are in NDP/sub R/ and can be ignored for true delay estimation, and the true delay estimates are on the average 15% less than the topological delay. The high level true delay estimates are accurate, as verified by comparing with the true delays obtained by gate-level timing analysis on actual implementations. Furthermore, results reveal that high level true delay estimation can be done very fast, even when gate-level true delay estimation becomes infeasible.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1088
Ending Page	1105
Page Count	18
File Size	2157781
File Format	PDF
ISSN	02780070
Volume Number	15
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-09-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay estimation High level synthesis Circuits Timing Resource management Clocks National electric code Hardware Processor scheduling Process design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Graphics and Computer-Aided Design Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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