NDLI: Design of testable VLSI circuits with minimum area overhead

Content Provider	IEEE Xplore Digital Library
Author	Chalasani, P.R. Bhawmik, S. Acharya, A. Palchaudhuri, P.
Copyright Year	1968
Abstract	One of the techniques used to tackle the increasing complexity of testing VLSI circuits is to incorporate built-in self-test (BIST) structures. However, incorporation of such BIST structures calls for increased area overhead due to additional logic gates and interconnections. It is very important to keep this area overhead to a minimum. The authors present a simple graph model of the area overhead minimization problem, for circuits into which BIST modifications are to be incorporated. Although the graph model does not account for a mixed type of BIST structure usage, it can be extended to include them at the cost of increased complexity.<>
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	1460
Ending Page	1462
Page Count	3
File Size	306487
File Format	PDF
ISSN	00189340
Volume Number	38
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Very large scale integration Built-in self-test Registers Automatic testing Integrated circuit interconnections Design for testability Galois fields Algorithm design and analysis Propulsion
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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