NDLI: Cost-Density Analysis of Interconnections

Content Provider	IEEE Xplore Digital Library
Author	Messner, G.
Copyright Year	1978
Abstract	A very rapid increase in the conductor density of various interconnecting substrates makes it desirable to have a uniform method for evaluation of their relative density capabilities. The derivation of one such method of evaluation, based on conductor density per unit of total area of the substrate, is made. This method permits a uniform density analysis of the entire interconnection spectrum from printed to integrated circuits. It is also useful in derivation of a price-density analysis and other figures of merits for assisting in the comparison of various packaging techniques. A description of a generalized approach for development of such a graphic price-density analysis is provided.
Sponsorship	IEEE Electronic Industries Alliance American Society of Mechanical Engineering (ASME) NBS SAE
Starting Page	143
Ending Page	151
Page Count	9
File Size	1257197
File Format	PDF
ISSN	01486411
Volume Number	10
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1987-06-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Wiring Conductors Integrated circuit packaging Large scale integration Printed circuits Graphics Very large scale integration Integrated circuit technology Density measurement
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Chip Carrier Applications

Chip-Module Package Interfaces

Ultra-High Density VLSI Modules

An Alternate Method of Fabricating Multilayer-Multichip Ceramic Substrates

Terminal and Cooling Requirements for LSI Packages

The VLSI Package-An Analytical Review

Electronic packaging in the 1990s-a perspective from Asia

Layer assignment for printed circuit boards and integrated circuits

Circuit-Board Packaging Considerations for Optimum Utilization of Chip Carriers

Cost-Density Analysis of Interconnections

Similar Documents

Chip Carrier Applications

Chip-Module Package Interfaces

Ultra-High Density VLSI Modules

An Alternate Method of Fabricating Multilayer-Multichip Ceramic Substrates

Terminal and Cooling Requirements for LSI Packages

The VLSI Package-An Analytical Review

Electronic packaging in the 1990s-a perspective from Asia

Layer assignment for printed circuit boards and integrated circuits

Circuit-Board Packaging Considerations for Optimum Utilization of Chip Carriers

Cost-Density Analysis of Interconnections