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Towards hybrid last level caches for chip-multiprocessors abstract — as cmp platforms are widely adopted.
| Content Provider | CiteSeerX |
|---|---|
| Abstract | more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distributed shared cache. In order to avoid hot-spots, cache lines are interleaved across the distributed shared cache slices using a hash function. However, as we increase the number of cores and cache slices in the platform, this also implies that most of data references go to remote cache slices, thereby increasing the access latency significantly. In this paper, we propose a hybrid last level cache, which has some amount of private space and some amount of shared space on each cache slice. For workloads with no sharing, the goal is to provide more hits into the local slice while still keeping the overall miss rate low. For workloads with sufficient sharing, the goal is to allow more sharing in the last-level cache slice. We present hybrid last-level cache design options and study its hit/miss rate behavior for a number of important server applications and multi-programmed workloads. Our simulation results on running multiprogrammed workloads based on SPEC CINT2000 as well as multithreaded workloads based on commercial server benchmarks (TPCC, SPECjbb, SAP and TPCE) show that this architecture is advantageous especially since it can improve the local hit rate significantly while keeping the overall miss rate similar to the shared cache. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Towards Hybrid Last Level Cache Spec Cint2000 Private Space Chip-multiprocessors Abstract Important Server Application Sufficient Sharing Overall Miss Rate Cache Line Multi-programmed Workload Hash Function Commercial Server Benchmark Local Slice Off-chip Memory Access Last-level Cache Slice Cache Slice Hybrid Last Level Cache Data Reference Cmp Platform Local Hit Rate Hit Miss Rate Behavior Simulation Result Last Level Cache Access Latency |
| Content Type | Text |
