NDLI: A CMOS Down-Conversion Mixer with High IIP2 and IIP3 for Multi-Band and Multiple Standards

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A CMOS Down-Conversion Mixer with High IIP2 and IIP3 for Multi-Band and Multiple Standards

Content Provider	ACM Digital Library
Author	Bampi, Sergio Cordova, David Fabris, Eric
Abstract	The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this paper a new highly linear CMOS mixer based on the Gilbert-cell topology is proposed. We introduce a second- and third-order distortion cancellation mechanisms using Post-distortion harmonic cancellation (PDHC). A Volterra series analysis of the transconductance stage of the proposed mixer is reported to show the effectiveness of the Post-distortion harmonic cancellation technique. Our design also implements a Dynamic Current Injection along with an LC filter in the switching stage to improve the Noise Figure. Electrical simulations are performed on extracted layout from our topology, using an IBM 0.13 μm CMOS process demonstrate the improvements on IIP3 and IIP2 in comparison to the conventional Gilbert cell. We achieved a conversion gain of 10.2dB with a NF of 11.89 dB for the design of a downconverter centered at 2GHz, with a low-IF of 500kHz. The mixer achieves an IIP2 and IIP3 of +55.51dBm and +10.85dBm respectively, while consuming only 5.28mW from a 1.2V supply.
Starting Page	1
Ending Page	7
Page Count	7
File Format	PDF
ISBN	9781450331562
DOI	10.1145/2660540.2660995
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-09-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Second- and third-order input intercept point (iip2 and iip3) High linearity Gilbert-cell mixers
Content Type	Text
Resource Type	Article

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