NDLI: Timing error handling on CGRAs

Content Provider	IEEE Xplore Digital Library
Author	Schweizer, T. Rosenstiel, W. Vaz Ferreira, L. Ritt, M.
Copyright Year	2013
Description	Author affiliation: Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil (Vaz Ferreira, L.; Ritt, M.) \|\| Fac. of Sci., Eberhard Karls Univ. Tubingen, Tubingen, Germany (Schweizer, T.; Rosenstiel, W.)
Abstract	Error-detection sequential (EDS) circuits are used to detect timing errors in electronic systems. This paper presents an EDS circuit that avoids the generation of false error signals on a coarse grained reconfigurable architecture (CGRA). In a first step we analyzed the timing error handling mechanism of EDS circuits and formulated - based on that analysis - the conditions that must be satisfied for EDS circuits to accomplish the avoidance of false error signals. In a second step we constructed an EDS circuit by means of these theoretical results and integrated this EDS circuit in a CGRA. Finally, we tested the CGRA by SPICE simulations. These simulations confirm that our EDS circuit implementation avoids false error signal generation on a CGRA.
Starting Page	1
Ending Page	6
File Size	424588
Page Count	6
File Format	PDF
e-ISBN	9781479920792
DOI	10.1109/ReConFig.2013.6732333
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Context Latches Hardware Delays Circuit faults Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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