NDLI: Additional Reviewers

Please wait, while we are loading the content...

2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

2012 International Conference on Reconfigurable Computing and FPGAs

2011 International Conference on Reconfigurable Computing and FPGAs

Table of Contents

Message from Chairs

Program Committee

Additional Reviewers

An Analysis of Implanted Antennas in Xilinx FPGAs

Adaptive Multi-client Network-on-Chip Memory

FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers

Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations

Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence

Resource Efficient Arithmetic Effects on RBM Neural Network Solution Quality Using MNIST

Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition

Object Recognition on a Chip: A Complete SURF-Based System on a Single FPGA

Measuring and Predicting Temperature Distributions on FPGAs at Run-Time

Heterogeneous Concurrent Error Detection (hCED) Based on Output Anticipation

Configuring Field-Programmable Robot Arrays

Identifying Merge-Beneficial Software Kernels for Hardware Implementation

A Reconfigurable Computing System Based on a Cache-Coherent Fabric

Multi-stream Regular Expression Matching on FPGA

Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers

Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs

An Architecture for Reconfigurable Multi-core Explorations

Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based Architectures

Hardware OS Communication Service and Dynamic Memory Management for RSoCs

Dynamic Processor Reconfiguration

GIMME - A General Image Multiview Manipulation Engine

Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures

A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing

FPGA Based Acceleration of Decimal Operations

MiniMIPS: An 8-Bit MIPS in an FPGA for Educational Purposes

Linking Formal Description and Simulation of Runtime Reconfigurable Systems

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems

Optimizing Decomposition-Based Packet Classification Implementation on FPGAs

Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing

Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable Computing

A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics

An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic Units

MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor

dcTPM: A Generic Architecture for Dynamic Context Management

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function

Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear Pairings

Area-Efficient FPGA Implementations of the SHA-3 Finalists

Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs

Decrypting HDCP-protected Video Streams Using Reconfigurable Hardware

Robustness Analysis of Different AES Implementations on SRAM Based FPGAs

Efficient Dual-Rail Implementations in FPGA Using Block RAMs

Versatile FPGA Architecture for Skein Hashing Algorithm

Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method

RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT

A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic Reconfigurability

FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information

Improving KLT in Embedded Systems by Processing Oversampling Video Sequence in Real-Time

Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel Estimation

Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation

High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel Emulation

Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO Systems

Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA

Design and Implementation of a Simplified Turbo Decoder for 3GPP2

Arbitrary Distribution Random Variable Generator for Channel Emulators

Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices

Reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip Architectures

Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration

Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration

The Impact of Global Routing on the Performance of NoCs in FPGAs

Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core

FPGA Bootstrapping on PCIe Using Partial Reconfiguration

From Instruction Traces to Specialized Reconfigurable Arrays

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays

A Self-Configuring TMR Scheme Utilizing Discrepancy Resolution

Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth

Scalable Models for Autonomous Self-Assembled Reconfigurable Systems

Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs

Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring Infrastructure

Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow

RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers

LiSARD: LabVIEW Integrated Softcore Architecture for Reconfigurable Devices

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture

Automatic Type Inference for Resynthesis on Hardware Description Languages

Enumeration of Costas Arrays Using GPUs and FPGAs

An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston Model

Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs

GPU vs FPGA: Example Application on White Light Interferometry

Spectral Method Characterization on FPGA and GPU Accelerators

Digital Talking Book Player for the Visually Impaired Using FPGAs

Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application

Toward All Optical Interconnections in Chip Multiprocessor (2)

Techniques for Dynamically Mapping Computations to Coprocessors

Reconfigurable Block Floating Point Processing Elements in Virtex Platforms

Publisher's Information

2010 International Conference on Reconfigurable Computing and FPGAs

2009 International Conference on Reconfigurable Computing and FPGAs

2008 International Conference on Reconfigurable Computing and FPGAs

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)

2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05)

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in