NDLI: Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Nam, Woongtae Son, Jihoon Shin, Hyunchol
Copyright Year	2015
Description	Author affiliation: High-Speed Integrated Circuits and Systems Lab., Kwangwoon University, Seoul, Korea (Nam, Woongtae; Son, Jihoon; Shin, Hyunchol)
Abstract	A 40GHz PLL synthesizer is designed in 65nm CMOS for a 60GHz sliding-IF RF transceiver for IEEE 802.11ad applications. For wide locking range, ILFD employs a 5-bit switched capacitor array and a inductive peaking at the injection FET. The ILFD's locking range is wider than the VCO's tuning range, which ensures the PLL can safely lock across the VCO's full tuning range. Also, a tuned buffer with a boosted Q load is employed to minimize unwanted interaction between the VCO and ILFD's operating frequencies, which also helps widen the PLL's locking range. The PLL synthesizer is designed in 65nm CMOS and its die area is 1.0×1.1mm2.
Starting Page	23
Ending Page	24
File Size	377147
Page Count	2
File Format	PDF
e-ISBN	9781467393089
DOI	10.1109/ISOCC.2015.7401633
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-02
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS PLL Voltage-controlled oscillators Synthesizers Frequency conversion Transceivers CMOS integrated circuits Synthesizer mm-Wave Phase locked loops Tuning Injection-locked frequency divider
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 58–63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS

A 60 GHz CMOS PLL synthesizer using a wideband injection-locked frequency divider with fast calibration technique

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

A 2.9mW 53.4–79.4GHz frequency-tracking injection-locked frequency divider with 39.2% locking range in 65nm CMOS

Dual-injection-locked ½ divider with optimized VCO loaded Q and current

Low-Power-Consumption Wide-Locking-Range Dual-Injection-Locked 1/2 Divider Through Simultaneous Optimization of VCO Loaded $Q$ and Current

A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop With A Multimode LC-Based ILFD

A wide-band CMOS injection-locked frequency divider

Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS

Similar Documents

A 58–63.6GHz quadrature PLL frequency synthesizer in 65nm CMOS

A 60 GHz CMOS PLL synthesizer using a wideband injection-locked frequency divider with fast calibration technique

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

A 2.9mW 53.4–79.4GHz frequency-tracking injection-locked frequency divider with 39.2% locking range in 65nm CMOS

Dual-injection-locked ½ divider with optimized VCO loaded Q and current

Low-Power-Consumption Wide-Locking-Range Dual-Injection-Locked 1/2 Divider Through Simultaneous Optimization of VCO Loaded $Q$ and Current

A Millimeter-Wave CMOS Triple-Band Phase-Locked Loop With A Multimode LC-Based ILFD

A wide-band CMOS injection-locked frequency divider

Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS