NDLI: Pattern Recognition without Tradeoffs: Scalable Accuracy with No Impact on Speed

Content Provider	IEEE Xplore Digital Library
Author	Dove, R.
Copyright Year	2009
Abstract	Automated recognition of patterns in data is constrained by tradeoffs among speed, cost, and accuracy. A new reconfigurable VLSI processor architecture decouples the speed/accuracy tradeoff, and renders the cost/accuracy tradeoff negligible, enabling new performance and new applications. The architecture features massively-parallel, dynamically configurable finite-state-machines which simultaneously process the same data stream. Low cost VLSI fabrication, unbounded scalability, and high speed constant-rate throughput independent of pattern number and complexity breaks current trade space constraints. This paper introduces features of the processor architecture responsible for the decoupling, and shows how current tradeoff structure is altered.
Starting Page	255
Ending Page	260
File Size	1295098
Page Count	6
File Format	PDF
ISBN	9780769535685
DOI	10.1109/CATCH.2009.31
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Couplings Fabrication Costs Terrorism Intrusion detection Very large scale integration Hardware-Assisted System Security Monitor Pattern recognition Computer security Field programmable gate arrays Phase detection pattern recognition
Content Type	Text
Resource Type	Article

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Pattern Recognition without Tradeoffs: Scalable Accuracy with No Impact on Speed