NDLI: A new 2.5-V CMOS 10.7-MHz IF circuit

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Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909)

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Greeting from conference chairs

Greeting from technical program chairs

Technical Program Committee

Steering Committee

Conference schedule

Technical program

Table of contents

An ultra-small RFID chip: /spl mu/-chip

Hardware architecture design for visual processing: present and future

SoC R&D trend for future digital life

Developing SoCs for digital consumer electronics

Academia-industry collaboration in SoC design education: wishes and reality

Table of contents

A 2.5-V, 14-bit MASH sigma-delta modulator for ADSL

Design techniques for CMOS micropower low-voltage switched-capacitor delta-sigma modulator

A low-power wide-bandwidth fully differential operational amplifier with current re-using feedforward frequency compensation

A new 2.5-V CMOS 10.7-MHz IF circuit

A single-chip CMOS single-conversion tunable low-IF receiver

Table of contents

A microcontroller IP generator for SOC platform

A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design

A low-power Booth multiplier using novel data partition method

Multiplierless multirate decimator/interpolator module generator

Design of LCD driver IP for SOC applications

Table of contents

A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops

A 2.2 GHz programmable DLL-based frequency multiplier for SOC applications

A DLL-based programmable clock generator using threshold-trigger delay element and circular edge combiner

An efficient all-digital built-in self-test for chargepump PLL

A phase-locked pulsewidth control loop with programmable duty cycle

Table of contents

An 8b 220 MS/s 0.25 /spl mu/m CMOS pipeline ADC with on-chip RC-filter based voltage references

An 8-bit 250MSPS CMOS pipelined ADC using open-loop architecture

A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter

An 8-bit 2-V 2-mW 0.25-mm/sup 2/ CMOS DAC

A 10-bit 210MHz CMOS D/A Converter for WLAN

Table of contents

A new output buffer for 3.3-V PCI-X application in a 0.13-/spl mu/m 1/2.5-V CMOS process

A PVT-insensitive CMOS output driver with constant slew rate

A high resolution, wide range digital impedance controller for high-speed SRAM interface

A four transistor CMOS active pixel sensor with high dynamic range operation

High speed digital smart image sensor with image compression function

Table of contents

A 1.8V 2.5-5.2 GHz CMOS dual-input two-stage ring VCO

A low phase noise wide tuning range CMOS quadrature VCO using cascade topology

Design of a new RF micromixer with low power and high performance in 0.25/spl mu/m CMOS technology

Independently controllable 3/sup rd/- and 5/sup th/-order analog predistortion linearizer for RF power amplifier in GSM

A CMOS VCO for 1V, 1GHz PLL applications

Table of contents

T4G: media processor including 3D graphics for mobile set based on configurable processor

A DSP engine for an extensible media embedded processor

A 32-bit 64-word 9-read, 7-write ported, noise and process variation-tolerant and wide-voltage-range-operative register file using 130 nm technology

ASIC design of IPSec hardware accelerator for network security

A reconfigurable public-key cryptography coprocessor

Interconnect delay aware RTL Verilog bus architecture generation for an SoC

A new RTL debugging methodology in FPGA-based verification platform

A parallel flop synchronizer for bridging asynchronous clock domains

Handshake-wave combined approach with runtime reconfiguration for designing a low latency asynchronous FIFO

Table of contents

A parallel-pipelined processor for fast fourier transform

Fast Fourier transform processor based on low-power and area-efficient algorithm

A novel implementation of cost-effective parallel-pipelined 8x8 DCT processor

Implementation of a bit-level super-systolic FIR filter

Design of bit manipulation accelerator for communication DSP

Iterative approximation on source and channel coding for images transmission over noisy channels

A word-based RSA crypto-processor with enhanced pipeline performance

AES coprocessor secure against power attacks

Table of contents

A 5Gbps CMOS LVDS transmitter with multi-phase tree type multiplexer

A 2.5Gbps serial-link data transceiver in a 0.35 /spl mu/m digital CMOS technology

1.0 Gbps LVDS transceiver design for LCD panels

A digitized LVDS driver with simultaneous switching noise rejection

A 2-Gbps CMOS adaptive line equalizer

FPGA implementation of an all-digital T/2-spaced QPSK receiver with Farrow interpolation timing synchronizer and recursive Costas loop

A hardware efficient 64-QAM low-IF transceiver baseband for broadband communications

An OFDM WLAN baseband receiver with space diversity

Table of contents

Direct access test scheme for IP core protection

RZ/NRZ dual-rail decoding scheme to reduce switching activities in asynchronous circuits

Three-dimensional round-robin scheduler for advanced input queuing switches

A technology migration method using rectangle-based layout conversion

False aggressors pruning using path sensitization and logic implications

Wire sizing considering skin effect for high frequency circuits

Preliminary experiments for power supply noise reduction using stubs

Table of contents

A miniaturized monolithic low noise amplifier for 2.4/5.2/5.7 GHz WLAN applications using InGaP/GaAs HBT technology

A 3.1-10.6 GHz CMOS cascaded two-stage distributed amplifier for ultra-wideband application

A 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier

A low power 5Gb/s transimpedance amplifier with dual feedback technique

Four-channel transimpedance amplifier array in a 0.35/spl mu/m CMOS technology for parallel optical interconnects

Table of contents

Area-efficient VLSI design of Reed-Solomon decoder for 10GBase-LX4 optical communication systems

A parallel multi-pattern PRBS generator and BER tester for 40/sup +/ Gbps Serdes applications

Symbol detection algorithm and implementation results for space-frequency OFDM transmit diversity scheme

A 1.7/spl sim/3.125Gbps clock and data recovery circuit using a gated frequency detector

A 14 GHz DLL based low-jitter multi-phase clock generator for low-band ultra-wideband application

Low-jitter transmission code for 4-PAM signaling in serial links

A VLSI architecture of G.SHDSL transceiver

Table of contents

A low-complexity method for distributed clocking on digital ASICs

A CMOS adiabatic logic for low power circuit design

Comparative study of static and dynamic D-type flip-flop circuits using InP HBTs

An implantable neural interface micro-stimulator chip with external controllability

Table of contents

5 GHz SiGe front-end components for WLAN applications

A dual-band IEEE 802.11a/b/g receiver front-end using half-IF and dual-conversion

A 6.25mm/sup 2/ 2.4GHz CMOS 802.11b transceiver

A CMOS dual-mode RF front-end receiver for GSM and WCDMA

Table of contents

Simultaneous current-mode bidirectional signaling for on-chip interconnection

High speed and low power global interconnect IP with differential transmission line and driver-receiver circuits

Arbitration latency analysis of the shared channel architecture for high performance multi-master SoC

Design and implementation of a routing switch for on-chip interconnection networks

Table of contents

A simple and fast PC interface for VLSI measurement

A novel high speed rfw scheme with no steady leakage for CP cell MRAM

A dynamically reconfigurable IP for data-intensive applications

A quadrilateral-object composer for binary images with reaction-diffusion cellular automata

A design of parallel matched filter with low calculation cost

Designing a TCP/IP core for power consumption analysis

Differential transmission line structure for over 10 Gbps signal transmission at global interconnect in Si ULSI

An approach for integration of demodulators for digital broadcasting

Reconfigurable RF circuit design for multi-band wireless chip

SysteMorph prototyping on DAP/DNA

An 8-bit 1 Gsps CMOS pipeline ADC

Design and measurement of on-chip di/dt detector circuit for power supply line

Design and implementation of word-parallel digital associative memories

Reduction of FFT circuit area for OFDM demodulator based on skipping-point representation

Low-power design for real-time image segmentation LSI and compact digital CMOS implementation

Design and optimization of CMOS current mode logic dividers

A neuron MOS variable logic circuit with the simplified circuit structure

A design of transponder IC for highly collision resistive RFID systems

Near field communication chip using PIM for bio MEMS sensors

Silicon Sea Belt

A new 2.5-V CMOS 10.7-MHz IF circuit

Content Provider	IEEE Xplore Digital Library
Author	Li, S.C. Hong-Sing Kao Yeong-Ren Wu
Copyright Year	2004
Description	Author affiliation: National Yunlin University of Science and Technology (Li, S.C.)
Abstract	This paper presents a low-voltage low-power 10.7-MHz IF circuit including limiting amplifier and FM/FSK demodulator. The limiting amplifier is implemented by cascaded of seven gain cells. The FM/FSK demodulator employs a new quadrature detector and is composed of an on-chip analog multiplier and an external tank phase shifter. The frequency to voltage conversion gain of the demodulator is 15 mVkHz. The sensitivity of the IF section including demodulator and limiting amplifier is -72 dBm. The current consumption of the proposed IF circuit is 4 mA from a single 2.5 V power supply. It occupies an active area of 580 μm X 1300 μm using 0.25-μm TSMC SP5M CMOS technology.
Sponsorship	IEEE Solid-State Circuit Soc. IEEE SSCS Region 10 Chapters
Starting Page	36
Ending Page	38
File Size	198461
Page Count	3
File Format	PDF
ISBN	078038637X
DOI	10.1109/APASIC.2004.1349397
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-05
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit technology Limiting Bit error rate Capacitors Frequency shift keying Detectors Voltage CMOS technology Phase detection Demodulation
Content Type	Text
Resource Type	Article

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