NDLI: A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Content Provider	IEEE Xplore Digital Library
Author	Nadeem, M. Wong, S. Kuzmanov, G. Shabbir, A.
Copyright Year	2009
Description	Author affiliation: Delft University of Technology, The Netherlands (Nadeem, M.; Wong, S.; Kuzmanov, G.) \|\| Eindhoven University of Technology, The Netherlands (Shabbir, A.)
Abstract	In this paper, we present a high-throughput, area-efficient, hardware accelerator for the deblocking filter in H.264/AVC video compression standard. In order to achieve this goal, we start with algorithmic optimization and propose a novel decomposition of the filter kernels for the deblocking filter. The proposed decomposition reduces the number of adders by 51% and thereby greatly reduces the area requirement for its implementation. Subsequently, at architecture level, while using two identical filtering units, the transpose units are realized by efficient reuse of hardware resources to further reduce the area requirement. The two filtering units process the horizontal and vertical edges of the macro-block simultaneously and therefore further enhance the throughput of the hardware accelerator. Several other optimization techniques, such as reuse of intermediate results, pipelining, and merging of processing blocks on critical path, result in a hardware accelerator for deblocking filter with high throughput at one hand and less area in terms of equivalent gates count on the other, when compared with existing state-of-the-art hardware accelerators in the literature. While working at clock frequency of 166 MHz, synthesized under 0.18 µm CMOS standard cell technology, it easily meets the throughput requirements of all the levels in H.264/AVC video coding standard and consumes only 12.06 K gates (excluding SRAM).
Starting Page	18
Ending Page	27
File Size	307452
Page Count	10
File Format	PDF
ISBN	9781424451692
DOI	10.1109/ESTMED.2009.5336814
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-15
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Filtering Merging Adaptive filters Video compression Throughput CMOS technology Hardware Automatic voltage control Kernel Pipeline processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Low-power, high-throughput deblocking filter for H.264/AVC

An Efficient Architecture for Deblocking Filter in H.264/AVC

Quadruple filtering schedule for H.264/AVC deblocking filter

Hardware architecture for H.264/AVC deblocking filter algorithm

A pipelined hardware architecture of deblocking filter in H.264/AVC

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in h.264/avc.

A memory efficient architecture of deblocking filter in H.264/AVC using hybrid processing order

An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering

A high-throughput low-power hardware architecture for H.264 deblocking filter

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC

Similar Documents

Low-power, high-throughput deblocking filter for H.264/AVC

An Efficient Architecture for Deblocking Filter in H.264/AVC

Quadruple filtering schedule for H.264/AVC deblocking filter

Hardware architecture for H.264/AVC deblocking filter algorithm

A pipelined hardware architecture of deblocking filter in H.264/AVC

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in h.264/avc.

A memory efficient architecture of deblocking filter in H.264/AVC using hybrid processing order

An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering

A high-throughput low-power hardware architecture for H.264 deblocking filter

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC