NDLI: Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results

Content Provider	IEEE Xplore Digital Library
Author	Kerckhof, S. Durvaux, F. Standaert, F.-X. Gerard, B.
Copyright Year	2013
Description	Author affiliation: ICTEAM/ELEN/Crypto Group, Univ. Catholique de Louvain, Louvain, Belgium (Kerckhof, S.; Durvaux, F.; Standaert, F.-X.; Gerard, B.)
Abstract	The use of Soft Physical Hash (SPH) functions has been recently introduced as a flexible and efficient way to detect Intellectual Property (IP) cores in microelectronic systems. Previous works have mainly investigated software IP to validate this approach. In this paper, we extend it towards the practically important case of FPGA designs. Based on experiments, we put forward that SPH functions-based detection is a promising and low-cost solution for preventing anti-counterfeiting, as it does not require any a-priori modification of the design flow. In particular, we illustrate its performances with stand-alone FPGA designs, re-synthetized FPGA designs, and in the context of parasitic IPs running in parallel.
Starting Page	7
Ending Page	12
File Size	222897
Page Count	6
File Format	PDF
ISBN	9781479905591
e-ISBN	9781479906017
DOI	10.1109/HST.2013.6581557
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Context Sensitivity Feature extraction Robustness IP networks Security Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Intellectual Property Protection for FPGA Designs with Soft Physical Hash Functions: First Experimental Results

An FPGA-based intellectual property protection method at physical design level

A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

A flexible design flow for software IP binding in commodity FPGA

Robust FPGA intellectual property protection through multiple small watermarks

Dynamic Intellectual Property Protection for Reconfigurable Devices

A multilevel fingerprinting method for FPGA IP protection

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits

Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results

Similar Documents

Intellectual Property Protection for FPGA Designs with Soft Physical Hash Functions: First Experimental Results

An FPGA-based intellectual property protection method at physical design level

A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing

A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs

A flexible design flow for software IP binding in commodity FPGA

Robust FPGA intellectual property protection through multiple small watermarks

Dynamic Intellectual Property Protection for Reconfigurable Devices

A multilevel fingerprinting method for FPGA IP protection

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits

Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results