NDLI: Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

Content Provider	IEEE Xplore Digital Library
Author	Jinghua Yang Kulkarni, N. Shimeng Yu Vrudhula, S.
Copyright Year	2014
Description	Author affiliation: Sch. of Comput., Inf. & Decision Syst. Eng. Arizona State Univ., Tempe, AZ, USA (Jinghua Yang; Kulkarni, N.; Shimeng Yu; Vrudhula, S.)
Abstract	Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.
Starting Page	39
Ending Page	44
File Size	267865
Page Count	6
File Format	PDF
ISBN	9781479963843
DOI	10.1109/NANOARCH.2014.6880500
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-08
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistance Resistors Low voltage Computer architecture Logic gates Delays Transistors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption

Yield-oriented energy and performance model for subthreshold circuits with V variations

Design of threshold logic gates using emerging devices

Differential high speed ultra low-voltage pass transistor boolean logic

An efficient CMOS rectifier with low-voltage operation for RFID tags

Low-Power Near-Threshold Design: Techniques to Improve Energy Efficiency Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wid

Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control

Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

Similar Documents

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption

Yield-oriented energy and performance model for subthreshold circuits with V variations

Design of threshold logic gates using emerging devices

Differential high speed ultra low-voltage pass transistor boolean logic

An efficient CMOS rectifier with low-voltage operation for RFID tags

Low-Power Near-Threshold Design: Techniques to Improve Energy Efficiency Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wid

Robust and energy-efficient asynchronous dynamic pipelines for ultra-low-voltage operation using adaptive keeper control

Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation