NDLI: Network interface to synchronize multiple packets on NoC-based Systems-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Matos, D. Costa, M. Carro, L. Susin, A.
Copyright Year	2010
Description	Author affiliation: Instituto de Informática - PPGC, Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, Brazil (Matos, D.; Costa, M.; Carro, L.; Susin, A.)
Abstract	The cores of a System-on-Chip (SoC) connected by Networks-on-Chip (NoCs) need interfaces to properly send and receive packets. However, in this interfacing, different situations can occur when heterogeneous cores are applied. Applications may require, for example, an irregular traffic behavior or present a large bandwidth variation. These situations may lead to problems in data synchronization. In this paper we show a simple and efficient synchronization solution, which although known in the literature, has not yet been applied to NoC-based systems scenario. Using a network interface as the synchronization mechanism, the proposed circuit handles data dependencies instead of letting each core solve the synchronization problems at higher levels. As case study, an H.264 video decoder was used to show the need and advantage of our approach. The proposed design is FIFO-based and can be applied when multiple packets from different sources need to be synchronized in a single destination. Simulations were performed to verify the functionality and efficiency of the synchronization solution. These interfaces were implemented in VHDL and synthesized using an 180nm CMOS technology.
Starting Page	31
Ending Page	36
File Size	1320819
Page Count	6
File Format	PDF
ISBN	9781424464692
e-ISBN	9781424464715
DOI	10.1109/VLSISOC.2010.5642627
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Switches Routing protocols Decoding CMOS integrated circuits Synchronization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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