NDLI: Keynotes

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2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013)

2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

2010 NASA/ESA Conference on Adaptive Hardware and Systems

2009 NASA/ESA Conference on Adaptive Hardware and Systems

2008 NASA/ESA Conference on Adaptive Hardware and Systems

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)

Second NASA/ESA Conference on Adaptive Hardware and Systems - Title page

Second NASA/ESA Conference on Adaptive Hardware and Systems - Copyright

Conference Organizers

Program Committee

List of reviewers

Wideband Dielectric Resonator Antenna with Reconfigurable Radiation Pattern

On the Applications for a Radiation Reconfigurable Antenna

Multi-Frequency Antenna design for Space-based Reconfigurable Satellite Sensor Node

Reconfigurable and Adaptive Antennas Using Materials with Variable Conductivity

Multiobjective Optimal Design of MEMS-Based Reconfigurable and Evolvable Sensor Networks for Space Applications

Renewal theory sleep time optimisation for scheduling events in Wireless Sensor Networks

Characterising Wireless Sensor Motes for Space Applications

Mixtrinsic Multi-Objective Reconfiguration of Evolvable Sensor Electronics

Data Requirements from Evolvable Sensor Networks for Homeland Security Problems

Following the Footsteps of Others: Techniques for Automatic Shoeprint Classification

Ensuring data integrity via ICmetrics based security infrastructure

Improving Key Distribution forWireless Sensor Networks

Multiresolution Hybrid Approaches for Automated Face Recognition

Normalizing Discrete Circuit Features with Statistically Independent values for incorporation within a highly Secure Encryption System

AES Embedded Hardware Implementation

An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performance

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications

A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm

H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture

Auto-adaptive reconfigurable architecture for scalable multimedia applications

A Configurable IP for Mode Decision of H.264/AVC Encoder

Adaptive Segmentation Technique For Object-Base MPEG-4 System

Systolic Array Based Architecture for Variable Block-Size Motion Estimation

System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design

A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure

Investigation of Reconfigurability for the Digital Backend of Ultra Wideband Receiver

High Performance Embedded Reconfigurable Concatenated Convolution- Puncturing Fabric for 802.16

Debug Support for Hybrid SoCs

A Novel Sampling Scheme for Efficient Analog to Digital Conversion

Analytical Modelling for Adaptive Multi-Purpose On-Chip Optical Interconnect

DWT Based Adaptive Threshold Determination in Embolic Signal Detection

Predictive Analysis for Robust Operation with Applications to Autonomous Biosensors

Adaptive Facial Behaviour using Selected Machine Learning Methods

Facial Image Associative Memory Model

A Reed-Solomon Algorithm for FPGA Area Optimization in Space Applications

An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment

Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application

Localized Payload Management Approach to Payload Control and Data Acquisition Architecture for Space Applications

Hybrid Communication Medium for Adaptive SoC Architectures

Programming an FPGA-based Super Computer Using a C-to-VHDL Compiler: DIME-C

Maxwell - a 64 FPGA Supercomputer

An Engineering Approach to Solving HPC Problems using FPGAs

The FPGA High-Performance Computing Alliance Parallel Toolkit

Automatic generation of ASICs

Synthesis of Multimode digital signal processing systems

Separation of Data flow and Control flow in Reconfigurable Multi-core SoCs using the Gannet Service-based Architecture

DNA and Protein Sequence Alignment with High Performance Reconfigurable Systems

A Reconfigurable Arithmetic Data-path Based On Regular Interconnection

A New Behavioural Power Modelling Approach for FPGA based Custom Cores

A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems

SoC Design Point Selection for Dynamic Adaptation under Continuously Varying Throughput Constraints

Hybrid Communication Medium for Adaptive SoC Architectures

Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform

Implementation of Finite State Machines on a Reconfigurable Device

Application of Self-Configurability for Autonomous, Highly-Localized Self-Regulation

Evolutionary Development of Generic Multipliers: Initial Results

Design of Self-organizing Bio-inspired Systems

Novel Embryonic Array with Neural Network Characteristics

Addressing the Metric Challenge: Evolved versus Traditional Fault Tolerant Circuits

evolFIR: Evolving redundancy-free FIR structures

MOVES: A Modular Framework for Hardware Evolution

Evolving Redundant Structures for Reliable Circuits - Lessons Learned

Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA

Extreme Temperature Electronics - from Materials to Bio-inspired Adaptation

Synthesis of Voltage Follower with Only CMOS Transistors Using Evolutionary Methods

Adaptive and Evolvable Hardware - A Multifaceted Analysis

A Power-Aware Algorithm for the Design of Reconfigurable Hardware during High Level Placement

A Multi-object GA Based Physical Placement Algorithm for Heterogeneous Dynamicaly Reconfigurable Arrays

Solving the even-n-parity problems using Best SubTree Genetic Programming

A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays

Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

An On-Chip Adaptive Spike Timing Based Offset Cancellation Scheme for Neuromorphic Sensing

On the Design of a Reconfigurable OTA-C Filter for Software Radio

A field programmable Gm-C filter array (FPAA) for online adaptation to environmental changes.

Programmable Analog VLSI Architecture Based upon Event Coding

A Population-oriented Architecture for Particle Swarms

A learning machine for resource-limited adaptive hardware

Evaluation of a New Platform For Image Filter Evolution

PERPLEXUS: Pervasive Computing Framework for Modeling Complex Virtually-Unbounded Systems

A Novel Hardware Architecture for Self-adaptive Systems

The Perplexus bio-inspired reconfigurable circuit

Multiagent approach to the distributed autonomous explorations

An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing

FPGA-Based Lookup Circuit for Session-Based IP Packet Classification

High-Speed IP Address Lookups Using Hardware Based Tree Structures

Novel Content Addressable Memory Architecture for Adaptive Systems

Trace algorithms for deeply integrated complex and hybrid SoCs

TRICODA - Complex Data Analysis and Condition Monitoring based onv Neural Network Model

An embedded sensor validation system for adaptive condition monitoring of a wind farms

ALT-DVS: Dynamic Voltage Scaling with Awareness of Leakage and Temperature for Real-Time Systems

Key Generation for Secure Inter-satellite Communication

A System Level Framework for Monitoring and Self Diagnosis in ESPACENET

Distributed Computing in Reconfigurable Picosatellite Networks

Automatic Synthesis of Fault Detection Modules for Mobile Robots

Using Relocatable Bitstreams for Fault Tolerance

Fault-recovery Non-FPGA-based Adaptable Computing System Design

Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip

A novel self-routing reconfigurable fault-tolerant cell array

Cellular Automata Based Binary Arithmetic for use on Self Repairing, Fault Tolerant Hardware

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)

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03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in