NDLI: HDTV in 1990s

Please wait, while we are loading the content...

2015 International Symposium on VLSI Technology, Systems and Applications

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

Proceedings of Technical Program of 2012 VLSI Technology, System and Application

Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications

Proceedings of 2010 International Symposium on VLSI Technology, System and Application

2009 International Symposium on VLSI Technology, Systems, and Applications

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2006 International Symposium on VLSI Technology, Systems, and Applications

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech).

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers

High-density ASICs with a three-dimensional CMOS process

An analytical model of threshold voltage and subthreshold swing for ultra-thin-film SOI MOSFETs

A new model on the mechanisms of high-frequency AC hot-carrier effects in MOS devices

A new MOSFET hot carrier model in SPICE feasible for VLSI reliability analysis

The improvement of I-V characteristics curve fitting by the modification of SPICE model-level 3

Depletion region formation at low temperatures

Advanced bipolar technology for the 1990s

Stacked capacitor cells for 64 MDRAM

A 13-bit analog interface for microprocessor-based systems

A single chip mixed digital/analog signal processor in 1.2 mu CMOS interfacing 4 analog subscriber lines to the PCM digital System 12 exchange

A transceiver for 800 kb/s full-duplex transmission over digital subscriber loops using a custom VLSI adaptive filter processor

An instruction set for a programmable signal processor dedicated to Viterbi detection

A design and implementation of multi-dimensional Y-C separation filters for NTSC TV signals

A video buffer controller design for HDTV/BISDN system

Experimental VLSI for HDTV and broadband fiber networks

A novel method to characterize and screen mobile ion contaminated nonvolatile memory products

Effects of the field-edge transistor on SOI MOSFETs

Implications of waveform and thickness dependence of SiO/sub 2/ breakdown on accelerated testing

Characterization of thin oxide damage during aluminum etching and photoresist ashing processes

Suppression of both sidewall injection and hot-carrier effects using laterally graded emitter in bipolar transistors

Determination of MOSFET's channel doping profile right up to SiO/sub 2//Si interface

Lateral distribution of hot-carrier-induced oxide charge and interface traps in MOSFET's

Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits

VLSI/ULSI research methodology in the US and Japan

GEAR: a general area router using planning approach

VLSI routing methodology for quadrupole metal sea-of-cells design

Using timed Boolean algebra to solve false path problem in timing analysis

Evaluation driven layout synthesis

Circuit optimization techniques in DROID

Simultaneous topology selection and timing assignment for LSI circuits based on semi-analytical delay-area expression

Transient sensitivity computation for waveform relaxation-based timing simulation

An integrated technology CAD environment

Approaches to high pin count and high power surface mount packages

The advanced improvement of PN mesa junction diode prepared by silicon-wafer direct bonding

Color CCD image sensor

Photo-excited dry cleaning for ULSI devices

A deep-submicrometer raised source/drain LDD structure fabricated using hot-wall epitaxy

Double spacer technique for titanium self-aligned silicidation technology

Al-plug stacked contact/via process for deep submicron CMOS multilayer metal technology

Suppression of boron penetration in BF/sub 2//sup +/-implanted polysilicon gated p-MOSFETs with reoxidized nitrided gate oxides

Cooling for high heat flux VLSI systems

A 32 bit microcontroller with an embedded flash EEPROM

Identification of DRAM sense amplifier imbalance using hot carrier evaluation

Circuit techniques for a wide world I/O path 64 Meg DRAM

A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs

A coded block adaptive neural network structure for pattern recognition VLSI

Multiprocessor-based video motion detection using adaptive neural systems

A scheme for implementation of neural networks with replicated receptive fields

A multichip analog neural network

DARPA artificial neural network technology program

Misfit stress in p/p+ epitaxial silicon wafers: effect and elimination

A high quality stacked thermal/LPCVD gate oxide for ULSI

Superior performance and reliability of MOSFETs with ultrathin gate oxides prepared by conventional furnace oxidation of Si in pure N/sub 2/O ambient

Pits reduction for poly Buffer LOCOS in VLSI fabrication

LOCOS-based isolation for 0.5 mu m device with PLD (polysilicon-spacered lateral diffusion) technology

Electron beam direct writing systems for 64 Mbit DRAM and beyond

Selective silylation and plasma patterning of photoresist in submicron lithography

Advanced i-line lithography for 0.5 mu m CMOS technology

Quarter- and sub-quarter-micron optical lithography

Gigascale integration (GSI) beyond 2001

The European microelectronics industry and its challenge for the nineties

Home electronics in the 1990s

1991 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No. 91TH0368-1)

Gallium arsenide and silicon for optical electronics: applications and technology trade-offs

SCOPE-a simultaneous contact and planarization etch process for low-cost high-performance CMOS applications

Large-area MOVPE growth for HEMT LSI

Characteristics of vertical p-channel MOSFETs for high density circuit application

Peeling-free tungsten polycide process and its application in DRAM fabrication

A 64 Mbit DRAM trench capacitor cell with field-plate isolation

A 0.5 mu m diode load 4 Mb SRAM technology using double-level Al plug metal process

A twin-tub CMOS using self-aligned channel-stop in conjunction with poly-buffer LOCOS for 1M/4M SRAM application

Low power, low voltage memories for portable electronics

DRAM technology trend and prospect

High performance CMOS VLSI chip set for synchronous optical transmission systems

ARES-architecture reinforcing superscalar

CMOS cell base implementation of the SPARC architecture

Modeling and design analysis of a workstation LAN server

TRAMPS/2: trace referenced analysis model of the personal system/2

The designs of two-level pipelined systolic arrays for recursive digital filters with maximum throughput rate

A systolic architecture for computing inverses in finite fields GF (2/sup m/)

The design of two-dimensional FIR and IIR filter architectures for HDTV signal processing

Wafer-scale systolic array for adaptive antenna processing

Channel mobility of GeSi quantum-well P-MOSFETs

Advanced bipolar circuits-a perspective

A new type of curvature-compensated CMOS bandgap voltage references

Accurate parametric interconnect modeling for high frequency LSI/VLSI circuits and systems

Design of pseudoexhaustive testable PLA with low overhead

A new pseudo-exhaustive test method

Parallel sequence fault simulation for synchronous sequential circuits

An event-driven incremental timing fault simulator

Extraction of defect characteristics for yield estimation using the double bridge test structure

On integrating control algorithms for buffer management and concurrency for parallel transaction processing systems

International Symposium on VLSI Technology, Systems and Applications,

HDTV in 1990s

Content Provider	IEEE Xplore Digital Library
Author	Ogi, K. Yamada, H.
Copyright Year	1991
Description	Author affiliation: Electron. Equipment Lab., Toshiba R&D Center, Kawasaki, Japan (Ogi, K.; Yamada, H.)
Abstract	HDTV has been the most promising candidate for the next generation electronic consumer products in the past ten years. However, the market is still not taking off. The main reason for the delay is the difficulty to obtain an agreement for a unified standard in the world. In 1990, CCIR published the recommendation of the HDTV standard. That will accelerate the market. On the other hand, LSI technology was not enough for realizing an economical HDTV receiver at the early development time, but there should be no problem in mid 1990s.
Starting Page	227
Ending Page	231
File Size	282698
Page Count	5
File Format	PDF
ISBN	078030036X
DOI	10.1109/VTSA.1991.246676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	HDTV Europe TV Satellite broadcasting Large scale integration Multimedia systems Computer displays Frequency Signal processing Digital signal processing
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in