NDLI: Proceedings International Verilog HDL Conference and VHDL International Users Forum

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Proceedings International Verilog HDL Conference and VHDL International Users Forum

Proceedings International Verilog HDL Conference and VHDL International Users Forum

Integrating of Verilog-HDL and VHDL languages in the SMASH/sup TM/ mixed-signal multi-level simulator

A case study of Compaq's simulation environment migration to Windows NT

Incremental compilation in the VCS environment

Transitioning to the new PLI standard

Implementing C designs in hardware: a full-featured ANSI C to RTL Verilog compiler in action

A procedural language interface for VHDL and its typical applications

VHDL 200x-requirements from testbench-view

Considerations on system-level behavioural and structural modeling extensions to VHDL

Practical FSM analysis for Verilog

Guidelines for safe simulation and synthesis of implicit style Verilog

Verilog nonblocking assignments demystified

Process-level modeling with VHDL

Tools for rapid construction of VHDL performance models for DSP systems

Modeling communication with Objective VHDL

Application of VHDL to software radio technology

Verilog plus C language modeling with PLI 2.0: The next generation simulation language

EP3: An extensible Perl preprocessor

A mixed-language simulator for concurrent engineering

A strategy for C-based verification

Reuse of models and testbenches at different levels of abstraction

ModelMaker: a tool for rapid modeling from device descriptions

Improving VHDL soft-cores reuse with software-like reviews and audits procedures

Overcoming the limitations of self-checking stimulus through the use of an ASIC mirror

A pseudorandom test environment

Networked object oriented verification with C++ and Verilog

A loosely coupled C/Verilog environment for system level verification

A functional test planning system for validation of DSP circuits modeled in VHDL

Scan parallel loading in VHDL

STG timing extensions and simulation

SAVANT/TyVIS/WARPED: components for the analysis and simulation of VHDL

Proceedings of Meeting on Verilog HDL (IVC/VIUF'97)

Proceedings. IEEE International Verilog HDL Conference

Proceedings. 1995 IEEE International Verilog HDL Conference

International Verilog HDL Conference

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in