NDLI: Comparative study of the radiation hardness of an analog CMOS pipeline, discrete MOS transistors and interface traps in MOS capacitors

Content Provider	IEEE Xplore Digital Library
Author	Bottcher, S. Coldewey, C. Croitoru, N. Seidman, A. Vogt, H.
Copyright Year	1996
Description	Author affiliation: II. Inst. fur Experimentalphys., Hamburg Univ., Germany (Bottcher, S.)
Abstract	The ZEUS experiment at HERA employs a custom made analog pipeline, manufactured with a 2 /spl mu/m CMOS process. The standard transistor layout was not sufficiently radiation hard. After introducing thin oxide extension and guard bands, the pipeline worked after irradiation, up to 500 krad, with only minor performance degradation. The performance of the pipeline and of discrete transistors was studied before and after irradiation. Additionally, interface traps were investigated on MOS capacitors. All devices were made with the same process. The degradation of transistor parameters was related to changes in the parameters of the pipeline. Most effects in the circuit could be explained by the observed threshold voltage shift in the transistors. Interface trap densities were measured on MOS capacitors in the lower part of the silicon bandgap, obtained under different bias conditions during irradiation. The observed interface trap density is low. The threshold voltage shift is dominated by fixed oxide charges.
Starting Page	50
Ending Page	56
File Size	575956
Page Count	7
File Format	PDF
ISBN	0780330935
DOI	10.1109/RADECS.1995.509750
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Degradation MOS capacitors Threshold voltage Manufacturing processes CMOS process Circuits Density measurement Silicon Photonic band gap
Content Type	Text
Resource Type	Article

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