NDLI: A 32 Mb/s fully-integrated read channel for disk-drive applications

Content Provider	IEEE Xplore Digital Library
Author	Kovacs, J. Palmer, W.
Copyright Year	1992
Description	Author affiliation: Analog Devices, Wilmington, MA, USA (Kovacs, J.; Palmer, W.)
Abstract	The authors describe a mixed-signal ASIC (application-specific integrated circuit) which integrates the entire disk-drive and read channel by combining bipolar and CMOS circuit techniques and taking advantage of the inherent device properties of each. The chip contains approximately 10000 devices fabricated in a 1.5- mu m 5-V-only BiCMOS process and implements the traditional peak detector architecture supporting zoned-bit recording applications. The 800-mW worst-case power dissipation and pin count of 52 are achieved by reducing the off-chip component requirement to that of bypass and coupling capacitors, the loop filter components for the AGC, and the phase-locked loops. Integration of the continuous-time filter eliminates high-accuracy inductors or capacitors for the lowpass filter/equalizer/differentiator networks. On-chip sampling capacitors for the servo peaks maintain matching between servo channels.
Starting Page	62
Ending Page	63
File Size	213143
Page Count	2
File Format	PDF
ISBN	0780305736
DOI	10.1109/ISSCC.1992.200411
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-02-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Filters Application specific integrated circuits Servomechanisms CMOS technology BiCMOS integrated circuits Detectors Disk recording Power dissipation Phase locked loops
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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