NDLI: A 4 b Josephson data processor chip

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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

Table of contents

1-volt operational amplifier with rail-to-rail input and output ranges

A 10-bit video BiCMOS track-and-hold

A wideband class-B video output driver

A 10 GHz operational amplifier in GaAs MESFET technology

A 50 MIPS (peak) 32/64 b microprocessor

A 64 b RISC microprocessor for a parallel computer system

CMOS implementation of a 32 b computer

1989 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. 36th ISSCC. First Edition (Cat. No.CH2684-9)

A 30 MIPS VLSI CPU

A 20 MIPS sustained 32 b CMOS microprocessor with 64 b data bus

Frame interline transfer CCD sensor for HDTV camera

A 1/3" format image sensor with refractory metal light shield for color video applications

A DSP-based watthour meter

An abuttable CCD imager for visible and X-ray focal plane arrays

A 310 k pixel bipolar imager (BASIS)

Merged CMOS/bipolar current switch logic

A single-ended BiCMOS sense circuit for digital circuits

A BiCMOS logic gate with positive feedback

A 76 MHz programmable logic sequencer

BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry

500 k transistor custom BiCMOS LSI using automated macrocell design

A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library

A 16 Mb mask ROM with programmable redundancy

A 5 V-only 256 kbit CMOS flash EEPROM

A 23 ns 256 K EPROM with double-layer metal and address transition detection

An experimental 4 Mb CMOS EEPROM with a NAND structured cell

120 ns 128 k*8 b/64 k*16 b CMOS EEPROMs

A 1 Mb flash EEPROM

An 8 b 40 MHz CMOS subranging ADC with pipelined wideband S/H

A CMOS 40 MHz 8 b 105 mW two-step ADC

A multistep ADC family with efficient architecture

A 12 b 500 ns subranging ADC

A 13-bit, 160 kHz, differential analog to digital converter

A self calibration technique for monolithic high-resolution D/A converters

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array

A 128k 6.5 ns access/5 ns cycle CMOS ECL static RAM

A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

A 9 ns 1 Mb CMOS SRAM

An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

An 8 ns 1 Mb ECL BiCMOS SRAM

A 20 ns 1 Mb CMOS burst mode EPROM

A 50 MHz 24 b floating-point DSP

A 40 MFLOPS 32-bit floating-point processor

A 40 MHz 64-bit floating-point co-processor

A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor

An 80 b, 6.7 MFLOPS floating-point processor with vector/matrix instructions

A 1,000,000 transistor microprocessor

The conception and evolution of digital audio

A 90 ns 100 K erase/program cycle megabit flash memory

A 3 Gb/s bipolar phase shifter and AGC amplifier

A GaAs MESFET 16*8 crosspoint switch

A single-chip digital signaling interface for the DSI intraoffice environment

A 16 Mb/s data detector and timing recovery circuit for token ring LAN

A rate adaption coprocessor for terminal adapters with U-interface modems

A 16 MBPS adapter chip for the token-ring local area network

A digital video signal processor for color image sensors

A codec LSI for HDTV signals

A realtime image processing chip set

A 1-GOPS CMOS programmable video signal processor

A 200 MIPS single-chip 1 k FFT processor

A 50 ns video signal processor

A single-chip 16-bit 25 ns realtime video/image signal processor

200 MHz 16-bit BiCMOS signal processor

A BiCMOS channelless masterslice with on-chip voltage converter

A 1.4 M-transistor CMOS gate array with 4 ns RAM

A CMOS sea-of-gates array with continuous track allocation

A 50 k-gate ECL array with substrate power supply

A 209 k-transistor ECL gate array with RAM

A high-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors

A GaAs MESFET macrocell array

A 200 MHz CMOS phase-locked loop with dual phase detectors

A GPS receiver with synthesized local oscillator

A digitally-controlled 20 b dynamic range BiCMOS stereo audio processor

A 12.5 MHz CMOS continuous time bandpass filter

A reconfigurable DMOS control chip for an electronic typewriter

Trimming analog circuits using floating-gate analog MOS memory

A symbolic simulator for analog circuits

An integrated 150 Vpp, 12 kV/ mu s class AB CRT-driving amplifier

A Si bipolar 15 GHz static frequency divider and 10 Gb/s multiplexer

A 23 ps/2.1 mW ECL gate

Low-temperature operation of silicon bipolar ECL circuits

A CMOS to 100 K ECL interface circuit

A 9 ns, low standby power CMOS PLD with a single-poly EPROM cell

A 500 MHz 16*16 complex multiplier using self-aligned gate heterostructure FET technology

A 4 b Josephson data processor chip

A 1.5 V DRAM for battery-based applications

200 Mb wafer memory

A 16 kb ferroelectric nonvolatile memory with a bit parallel architecture

A 60 ns 3.3 V 16 Mb DRAM

A 55 ns 16 Mb DRAM

A 45 ns 16 Mb DRAM with triple-well structure

A 25 ns 4 Mb CMOS SRAM with dynamic bit line loads

A single chip BiMOS telephone set

An ANSI standard ISDN transceiver chip set

An ISDN echo-cancelling transceiver chip for 2B1Q coded U-interface

2B1Q transceiver for the ISDN subscriber loop

A front-end processor for modems

An acoustic echo canceler

A mixed analog-digital secondary channel FSK modem

A single-chip 2B1Q U-interface transceiver

1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1975 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1974 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1971 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1970 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1969 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1968 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1967 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1966 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1965 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1962 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1961 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1959 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1958 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1957 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1956 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

1955 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

A 4 b Josephson data processor chip

Content Provider	IEEE Xplore Digital Library
Author	Hatano, Y. Mori, H. Yamada, H. Nagaishi, H. Nakane, H. HIrano, M. Kawabe, U.
Copyright Year	1989
Description	Author affiliation: Hitachi Ltd., Tokyo, Japan (Hatano, Y.; Mori, H.; Yamada, H.; Nagaishi, H.; Nakane, H.; HIrano, M.; Kawabe, U.)
Abstract	The authors describe a 4-bit Josephson data processor chip featuring on-chip control and data paths and near-GHz capability. It is a closed, stand-alone chip comprising a 4-bit data path and a control path and is aimed at high-speed digital signal processing. The die is 0.5 mm square, including pads, is fabricated using 2.5- mu m-rule Nb/AlO/sub x//Nb technology, and consists of 8454 Josephson junctions and 9027 resistors. The cross-shaped junction structure realizes critical current scattering of +or-6%, and a junction characteristic voltage V/sub m/ of 50 mV. A block diagram of the Josephson data processor is shown.
Starting Page	234
Ending Page	235
File Size	552690
Page Count	2
File Format	PDF
DOI	10.1109/ISSCC.1989.48270
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors Voltage Flip-flops Crosstalk Delay Radio frequency Clocks Niobium Registers Read only memory
Content Type	Text
Resource Type	Article

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