NDLI: Evaluating the effects of cache redundancy on profit

Content Provider	IEEE Xplore Digital Library
Author	Das, A. Ozisikyilmaz, B. Ozdemir, S. Memik, G. Zambreno, J. Choudhary, A.
Copyright Year	2008
Description	Author affiliation: Electr. Eng. & Comput. Sci. Dept., Northwestern Univ., Evanston, IL (Das, A.; Ozisikyilmaz, B.; Ozdemir, S.; Memik, G.; Choudhary, A.) \|\| Electr. & Comput. Eng. Dept., Iowa State Univ., Ames, IA (Zambreno, J.)
Abstract	Previous works in computer architecture have mostly neglected revenue and/or profit, key factors driving any design decision. In this paper, we evaluate architectural techniques to optimize for revenue/profit. The continual trend of technology scaling and sub-wavelength lithography has caused transistor feature sizes to shrink into the nanoscale range. As a result, the effects of process variations on critical path delay and chip yields have amplified. A common concept to remedy the effects of variations is speed-binning, by which chips from a single batch are rated by a discrete range of frequencies and sold at different prices. An efficient binning distribution thus decides the profitability of the chip manufacturer. We propose and evaluate a cache-redundancy scheme called substitute cache, which allows the chip manufacturers to modify the number of chips in different bins. Particularly, this technique introduces a small fully associative array associated with each cache way to replicate the data elements that will be stored in the high latency lines, and hence can be effectively used to boost up the overall chip yield and also shift the chip binning distribution towards higher frequencies. We also develop models based on linear regression and neural networks to accurately estimate the chip prices from their architectural configurations. Using these estimation models, we find that our substitute cache scheme can potentially increase the revenue for the batch of chips by as much as 13.1%.
Starting Page	388
Ending Page	398
File Size	609069
Page Count	11
File Format	PDF
ISBN	9781424428366
ISSN	10724451
DOI	10.1109/MICRO.2008.4771807
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-08
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Manufacturing Frequency Profitability Design optimization Costs Design engineering Computer architecture Lithography Transistors Delay effects Fault-tolerance Device Variability Process Variations Cache Architecture Profit and Revenue
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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