NDLI: Design of high speed low power multiplier using Reversible logic: A Vedic mathematical approach

Content Provider	IEEE Xplore Digital Library
Author	Rakshith, T.R. Saligram, Rakshith
Copyright Year	2013
Description	Author affiliation: Dept. of Electronics and Communication, B M S College Of Engineering, Bangalore, India (Saligram, Rakshith) \|\| Dept. of Telecommunication, R V College Of Engineering, Bangalore, India (Rakshith, T.R.)
Abstract	Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.
Sponsorship	IEEE India Council ED Chapter
Starting Page	775
Ending Page	781
File Size	1273630
Page Count	7
File Format	PDF
ISBN	9781467349215
e-ISBN	9781467349222
DOI	10.1109/ICCPCT.2013.6528848
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-20
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless communication Multiplexing Reversible Logic Urdhva Tiryakbhayam Heating Vedic Multiplier Logic gates Total Reversible Logic Implementation Cost Quantum Cost Integrated circuit modeling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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