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Content Provider | IEEE Xplore Digital Library |
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Author | Tong Zhou Song Guo Yuanwu Lei Yong Dou |
Copyright Year | 2015 |
Description | Author affiliation: Nat. Lab. for Parallel & Distrib. Process., Nat. Univ. of Defense Technol., Changsha, China (Tong Zhou; Song Guo; Yuanwu Lei; Yong Dou) |
Abstract | This paper aimed to improve MIMO detector's performance in both throughput and cost. Thus, it presents a FPGA architecture implementation for the SQRD detection in a 4 × 4 16-QAM MIMO wireless communication systems. The exploitation of fine-grained parallelism and coarse-grained parallelism strategies are responsible for bettering the performance of the implementation. Besides, this paper proposes a method to ensure the correctness of the implementation of time-sharing modules, which is general and applicable to any MIMO detector implementation. The work results in a real-time FPGA-based implementation delivering 32 MSQRD/s with 5.2 us latency and lowering more than 50\% cost in hardware resources on a Xilinx Virtex6. |
Starting Page | 394 |
Ending Page | 398 |
File Size | 415948 |
Page Count | 5 |
File Format | |
ISBN | 9781467381253 |
e-ISBN | 9781467381260 |
DOI | 10.1109/CompComm.2015.7387603 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2015-10-10 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | FPGA SQRD Detectors Computer architecture Parallel processing Throughput MIMO Hardware Parallel architecture Matrix decomposition Time-sharing |
Content Type | Text |
Resource Type | Article |
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