NDLI: New approach for multiple vector reduction on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Jinzhu Zhang Minglu Zhang Hua He Qingzeng Song
Copyright Year	2015
Description	Author affiliation: Sch. of Mech. Enineering, Hebei Univ. of Technol., Tianjin, China (Minglu Zhang) \|\| Sch. of Sci., Hebei Univ. of Technol., Tianjin, China (Hua He) \|\| Sch. of Mech. Eng., Hebei Univ. of Technol., Tianjin, China (Jinzhu Zhang) \|\| Sch. of Comput. Sci. & Software Eng., Tianjin Polytech. Univ., Tianjin, China (Qingzeng Song)
Abstract	Multiple vector reduction is one of the most fundamental and widely used operations in scientific computation. It is an attractive option to accelerate this computation program using FPGA as hardware accelerators. However, core operator of the vector reduction is usually floating point units which are often deeply pipelined, improper control may destroy the benefit from pipelining or impose unrealistic buffer requirements. In this paper, we propose a new approach on FPGA for multiple vector reduction. The design contributes an interleave-based vector reduction approach with high pipeline utilization. The proposed approach significantly simplifies the control units of the vector reduction operations. The sparse matrix vector multiplication is implemented as an application example in this paper.
Starting Page	427
Ending Page	430
File Size	115953
Page Count	4
File Format	PDF
ISBN	9781479972838
e-ISBN	9781479972845
DOI	10.1109/ICEIEC.2015.7284574
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-14
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Hardware Sparse matrices Acceleration Field programmable gate arrays Clocks Pipeline processing
Content Type	Text
Resource Type	Article

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