NDLI: High Performance BIST PLL approach for VCO testing

Content Provider	IEEE Xplore Digital Library
Author	Toihria, I. Ayadi, R. Masmoudi, M.
Copyright Year	2014
Description	Author affiliation: Nat. Sch. Eng. of Sfax (ENIS), Univ. of Sfax, Sfax, Tunisia (Toihria, I.; Masmoudi, M.) \|\| Nat. Sch. Eng. of Sfax (ENIS) Sfax, Univ. of Sfax, Sfax, Tunisia (Ayadi, R.)
Abstract	RF and mixed signal IC testing is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. This paper focuses on certain mixed signal IC that is phase locked loop (PLL). A novel BIST (Built-In-Self-Test) approach is developed for RF PLL; it is particularly applied for testing the VCO block. The proposed BIST schema doesn't break the loop to include test circuit in the PLL design stage which is achieved with minimal degradation characteristics of PLL. The key advantage of this technique is that it uses an internal test signal for evaluating the test procedure. The presented architecture uses the existing elements for measuring and testing in order to reduce the area overhead for BIST schema, solves the analog nodes loading problem and improves the test accessibility. The test output generated is a purely digital signal. The BIST method enables the detection of catastrophic and many parametric faults affected the VCO by measuring its oscillation frequency response. To evaluate the effectiveness of proposed BIST approach, a fault simulation results indicate the characteristic of the BIST structure that is high fault coverage of 100%.
Sponsorship	ATSI
Starting Page	517
Ending Page	522
File Size	817385
Page Count	6
File Format	PDF
ISBN	9781479948888
DOI	10.1109/ATSIP.2014.6834669
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-17
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	PLL High Fault Coverage VCO Voltage-controlled oscillators IC Testing Built-in self-test BIST (Built In Self Test) Vectors Circuit faults Phase locked loops
Content Type	Text
Resource Type	Article

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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