NDLI: Design of online testable fast divider

Content Provider	IEEE Xplore Digital Library
Author	Nagamani, A.N. Supreetha, N.J.
Copyright Year	2013
Description	Author affiliation: PES Inst. of Technol., Bangalore, India (Nagamani, A.N.; Supreetha, N.J.)
Abstract	Division is the critical arithmetic operation for high speed digital design like 3-D graphics and DSP applications. Faster the arithmetic operation so is the application and power efficiency of such operations leads to durability of the system. But VLSI implementation of division is generally slower and more area consuming than the other three basic arithmetic operations such as addition, subtraction and multiplication. Owing to its advantages over PTL, CMOS logic based divider proves 92% faster and 99% power efficient with 25% area overhead. Also the complexity of the divider circuit causes its testing a bottleneck to system testing. Here we propose optimized non-restoring division algorithm with remainder decoding using CMOS logic in 90nm technology. Also we demonstrate the application of BIST to larger divider circuit. We compare the use of conventional LFSR and Cellular Automation for PRPG. And for output compression and signature analysis MISRs seem to be very effective due to their less area overhead.
Sponsorship	IEEE Bangalore Sect. PHO Chapt.
Starting Page	1
Ending Page	6
File Size	435528
Page Count	6
File Format	PDF
ISBN	9781479910823
e-ISBN	9781479910854
DOI	10.1109/C2SPCA.2013.6749441
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	LFSR - Linear Feedback Shift Register Circuit faults PRPG - Pseudo Random Pattern Generation MISR - Multiple Input Signature Register PTL -Pass Transistor Logic BIST - Built-in Self-Test CA-Cellular Automation Polynomials CMOS integrated circuits Delays Transistors Adders Testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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