NDLI: A hybrid reconfigurable cryptographic processor with RSA and SEA

Content Provider	IEEE Xplore Digital Library
Author	Chitra, A. Sheeba, T.B.
Copyright Year	2012
Description	Author affiliation: Dept. of Electronics and communications., RMK Engineering College, Anna University of Technology, Kaverapettai, Chennai, India (Chitra, A.; Sheeba, T.B.)
Abstract	Data security is in Demand in everyday life of Digital World, since Digital data's can be reproduced much easily. To achieve the maximum security required a Parallel Processing, User Reconfigurable Cryptographic RISC Microprocessor is proposed in our paper. Rather than protecting the data using tools and external codes, a microprocessor is specially designed in our project to offer maximum digital security. Cryptographic processor can be classified either as asymmetric cryptography or a symmetric cryptography processor. Asymmetric cryptography has the advantage of Reception security but has the limitation of High resource Utilization. And a symmetric cryptography processor has the limitation of single key security but comparatively has the advantages of low area, resource and power consumption. Thus in this project we are proposing Hybrid architecture in which both the advantage of asymmetric and symmetric cryptographies are combined. For implementation, Asymmetric RSA cryptography and a symmetric lightweight SEA encryption is combined to mutate a reconfigurable Cryptographic processor.
Starting Page	428
Ending Page	433
File Size	445465
Page Count	6
File Format	PDF
ISBN	9781467315999
e-ISBN	9781467316019
DOI	10.1109/ICRTIT.2012.6206750
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Cryptographic Processor Reconfigurable Architecture Data security Elliptic curve cryptography Reduced instruction set Computer (RISC) Encryption Registers Power dissipation Rivest-Shamir-Adelman (RSA) cryptosystem Scalable Encryption Algorithm (SEA)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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