NDLI: CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques

Content Provider	IEEE Xplore Digital Library
Author	Sheng Li Ke Chen Jung Ho Ahn Brockman, J.B. Jouppi, N.P.
Copyright Year	2011
Description	Author affiliation: Hewlett-Packard Labs (Sheng Li; Jouppi, N.P.) \|\| Seoul National University (Jung Ho Ahn) \|\| University of Notre Dame (Ke Chen; Brockman, J.B.)
Abstract	This paper introduces CACTI-P, the first architecture-level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTI-P supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables in-depth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTI-P in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.
Starting Page	694
Ending Page	701
File Size	489247
Page Count	8
File Format	PDF
ISBN	9781457713996
ISSN	10923152
e-ISBN	9781457714009
e-ISBN	9781457713989
DOI	10.1109/ICCAD.2011.6105405
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Switching circuits Random access memory Leakage current Logic gates Integrated circuit modeling Timing manycore processor Leakage power management power-gating circuit modeling SRAM cache
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software Computer Science Applications

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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