NDLI: On behavioral model equivalence checking for large analog/mixed signal systems

Content Provider	IEEE Xplore Digital Library
Author	Singh, A. Peng Li
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering Texas A&M University, College Station, TX 77843 (Singh, A.; Peng Li)
Abstract	This paper presents a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as PLLs, ADCs and I/O's. We verify the equivalence between a behavioral model and its electrical implementation over a limited, but highly likely, input space defined as the Constrained Behavioral Input Space. Further, we clearly distinguish between the behavioral and electrical domains and define mappings between the two domains to allow for calculation of deviation between the behavioral and electrical implementation. The verification problem is then formulated as an optimization problem which is solved by interfacing a SQP based optimizer with commercial circuit simulation tools. The proposed methodology is then applied for equivalence checking of a PLL as a test case.
Starting Page	55
Ending Page	61
File Size	1073902
Page Count	7
File Format	PDF
ISBN	9781424481934
ISSN	10923152
e-ISBN	9781424481941
DOI	10.1109/ICCAD.2010.5651402
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit modeling Voltage-controlled oscillators Optimization Phase locked loops Mathematical model Computational modeling SPICE System Verification Analog Circuits Formal verificiation Equivalence Checking
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software Computer Science Applications

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