NDLI: Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization

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2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers

2008 IEEE/ACM International Conference on Computer-Aided Design

2007 IEEE/ACM International Conference on Computer-Aided Design

2006 IEEE/ACM International Conference on Computer Aided Design

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

1999 IEEE/ACM International Conference on Computer-Aided Design. [Front Cover and Table of Contents]

Marsh:min-area retiming with setup and hold constraints

OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic

Bit-level arithmetic optimization for carry-save additions

Attractor-repeller approach for global placement

Cell replication and redundancy elimination during placement for cycle time optimization

Concurrent logic restructuring and placement for timing closure

Implicit enumeration of strongly connected components

Least fixpoint approximations for reachability analysis

Lazy group sifting for efficient symbolic state traversal of FSMs

Efficient manipulation algorithms for linearly transformed BDDs

Noise analysis of non-autonomous radio frequency circuits

New methods for speeding up computation of Newton updates in harmonic balance

Design and optimization of LC oscillators

Modeling and simulation of the interference due to digital switching in mixed-signal ICs

Provably good algorithm for low power consumption with dual supply voltages

A novel design methodology for high performance and low power digital filters

A bipartition-codec architecture to reduce power in pipelined circuits

AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths

Analytical approach to custom datapath design

An integrated algorithm for combined placement and libraryless technology mapping

Timing-driven partitioning for two-phase domino and mixed static/domino implementations

Implication graph based domino logic synthesis

Synthesis for multiple input wires replacement of a gate for wiring consideration

Transient sensitivity computation for transistor level analysis and tuning

An efficient method for hot-spot identification in ULSI circuits

A scalable substrate noise coupling model for mixed-signal ICs

Towards true crosstalk noise analysis

SAT based ATPG using fast justification and propagation in the implication graph

Techniques for improving the efficiency of sequential circuit test generation

Concurrent D-algorithm on reconfigurable hardware

A new heuristic for rectilinear Steiner trees

An implicit connection graph maze routing algorithm for ECO routing

The associative-skew clock routing problem

Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays

Optimal P/N width ratio selection for standard cell libraries

Performance optimization under rise and fall parameters

Performance optimization using separator sets

Factoring logic functions using graph partitioning

TICER: Realizable reduction of extracted RC circuits

Realizable reduction for RC interconnect circuits

RLC interconnect delay estimation via moments of amplitude and phase response

Practical considerations for passive reduction of RLC circuits

Interconnect parasitic extraction in the digital IC design methodology

Cycle time and slack optimization for VLSI-chips

Clock skew scheduling for improved reliability via quadratic programming

Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation

Function inlining under code size constraints for embedded processors

Function unit specialization through code analysis

Lower bound on latency for VLIW ASIP datapaths

Interface and cache power exploration for core-based embedded system design

Dynamic power management using adaptive learning tree

Analytical macromodeling for high-level power estimation

Parameterized RTL power models for combinational soft macros

Validation and test generation for oscillatory noise in VLSI interconnects

Fault modeling and simulation for crosstalk in system-on-chip interconnects

Robust optimization based backtrace method for analog circuits

A methodology for correct-by-construction latency insensitive design

What is the cost of delay insensitivity?

Synthesis of asynchronous control circuits with automatically generated relative timing assumptions

Direct synthesis of timed asynchronous circuits

Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication

Power minimization using system-level partitioning of applications with quality of service requirements

Worst-case analysis of discrete systems

Integrated floorplanning and interconnect planning

Buffer block planning for interconnect-driven floorplanning

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

The Chebyshev expansion based passive model for distributed interconnect networks

Model reduction for DC solution of large nonlinear circuits

Efficient model reduction of interconnect via approximate system gramians

A framework for testing core-based systems-on-a-chip

Test scheduling for core-based systems

Partial BIST insertion to eliminate data correlation

A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning

Throughput optimization of general non-linear computations

Optimal allocation of carry-save-adders in arithmetic optimization

Regularity extraction via clan-based structural circuit decomposition

Repeater insertion in tree structured inductive interconnect

Interconnect scaling implications for CAD

Is wire tapering worthwhile?

Electromagnetic parasitic extraction via a multipole method with hierarchical refinement

Virtual screening: a step towards a sparse partial inductance matrix

A wide frequency range surface integral formulation for 3-D RLC extraction

An approach for improving the levels of compaction achieved by vector omission

Deep submicron defect detection with the energy consumption ratio

Efficient diagnosis of path delay faults in digital logic circuits

Memory bank customization and assignment in behavioral synthesis

Memory binding for performance optimization of control-flow intensive behaviors

Improved interconnect sharing by identity operation insertion

Formal specification and verification of a dataflow processor array

Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization

Synchronous equivalence for embedded systems: a tool for design exploration

On the global fanout optimization problem

LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay

Optimum loading dispersion for high-speed tree-type decision circuitry

Symbolic functional and timing verification of transistor-level circuits

Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis

Functional timing optimization

Timing-safe false path removal for combinational modules

JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations

FunState-an internal design representation for codesign

Fast performance analysis of bus-based system-on-chip communication architectures

Probabilistic state space search

Improving coverage analysis and test generation for large designs

Modeling design constraints and biasing in simulation using BDDs

Copyright protection of designs based on multi source IPs

Localized watermarking: methodology and application to operation scheduling

Copy detection for intellectual property protection of VLSI designs

Design of a set-top box system on a chip

On the rapid prototyping and design of a wireless communication system on a chip

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

Proceedings of International Conference on Computer Aided Design

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

IEEE/ACM International Conference on Computer-Aided Design

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

1992 IEEE/ACM International Conference on Computer-Aided Design

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

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