NDLI: A VLSI Decoder for the Golden code

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2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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2010 17th IEEE International Conference on Electronics, Circuits and Systems

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

2008 15th IEEE International Conference on Electronics, Circuits and Systems

2007 14th IEEE International Conference on Electronics, Circuits and Systems

2006 13th IEEE International Conference on Electronics, Circuits and Systems

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Table of contents

Distributed RLC Interconnect: Analytical Modelling Expressions for Crosstalk Noise Estimation

A New RF SiCMOS SDD Model for Quantifying Individual Contribution to Distortion from Transistor's Nonlinear Parameters

Noise Modeling For Charge Amplification and Sampling

General Model for the Deployment of Time-Delay Elements in Transistorized Electronic Circuits

Multiconductor Transmission Lines Sensitivity via Two-Dimensional Laplace Transform

Design and Analysis of A Class-E Frequency-Controlled Transcutaneous Energy Transfer System

Multiparameters monitoring for long term in-vivo characterization of electrode-tissues contacts

An Efficient Micro-Stimulator Array Using Unitary-Size DAC With Adiabatic Baseband Scheme

Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem

Comparison of Transconductance Reduction Techniques for the Design of a Very Large Time-Constant CMOS Integrator

Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers

Quadrature Mismatch Shaping with a Complex, Data Directed Swapper

Design of Cascaded Continuous-Time Sigma-Delta Modulators

Use of the Step Invariant Transform to Design a 2nd Order Continuous Time Complex Sigma-Delta ADC

Sigma-Delta Solutions for Future Wireless Handields

Analysis of Wideband CMOS Low Noise Amplifiers using current-reuse configuration

Concurrent Dual-Band Low Noise Amplifier for 802.11a/g WLAN applications

Design and Implementation of BiFET LNAs for W-CDMA / IEEE 802.11a Applications

Inversion-Coefficient Based Design of RF CMOS Low-Noise Amplifiers

A Low-Voltage CMOS LNA Design Utilizing the Technique of Capacitive Feedback Matching Network

Differential-Mode/Common-Mode Feedforward Transconductor for Low-Voltage Gm-C filters

A High-Linear Low-voltage CMOS Tunable Transconductor for VHF Filtering

A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency

Automatic Tuning of Continuous Time Adaptive Bandpass Filter

Oscillation-Based Test Structure and Method for OTA-C Filters

An FFT Core for DVB-T/DVB-H Receivers

An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications

A Methodology for Design Space Exploration in Embedded DSP Applications

Design and Implementation of a Correlation-based DSP Software for Narrowband Power Line Communication Receiver

A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor

Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless Communications

A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCs

Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers

A 2nd Order 1-bit Complex Switched Capacitor Sigma-Delta ADC with 90dB SNDR in a 180kHz Bandwidth

A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a Novel Folder Reduction Technique

An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor

CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver

An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture

Rethinking Processor Design: Parameter Correlations

Supporting A Dynamic Program Signature: An Intrusion Detection Framework for Microprocessors

Power Modeling and Efficient FPGA Implementation of Color Space Conversion

An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs

Design Space Exploration of Division over GF(2m) on FPGA: A Digit-Serial Approach

FPGA Implementations of a Simplified Retinex Image Processing Algorithm

High Throughput Architecture of JPEG Compressor for Color Images Targeting FPGAs

Multi-Mode Wideband Voltage Controlled Oscillators

High-Performance VCO for 5-GHz WLANs in 0.35 μm CMOS Standard Technology

Design of a 1.2 V Low Phase Noise 1.6 GHz CMOS Buffered Quadrature Output VCO with Automatic Amplitude Control

Analysis of Harmonic Distortion in the Colpitts Oscillator

A Design Approach for Low Phase Noise 5GHz Complementary Quadrature Oscillator

NMOS Low Drop-Out Regulator with Dynamic Biasing

Novel Approach to Low-Voltage Low-Power Bandgap Reference Voltage in Standard CMOS Process

Design of fuel-cell powered DC-DC converter for portable applications in digital CMOS technology

High Linear Voltage References for on-chip CMOS Temperature Sensor

Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory

Characterization of In-Phase/Quad-Phase Digital Downconversion Via Special Sampling Scheme

Multiple Input Digital Arbiter with Timestamp Assignment for Asynchronous Sensor Arrays

Efficient Circuitry for Computing τ-adic Non-Adjacent Form

Time-Domain Synthesis of IIR Phase Equalizers

Spread Spectrum PWM Signal Generator for Fully Digital Audio Amplifier

Explaining Hysteresis in Electronic Circuits: Robust Simulation and Design Examples

A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications

Hazard Free Sawtooth Oscillator and Its Application in Ultra Low Current Monitoring

A wide bandwidth voltage-follower with low distortion and high slew rate

A Novel CMOS Mini-LVDS Receiver for Flat-Plane Application

Design Guidelines for Two-Stage Cascode-Compensated Operational Amplifiers

Simple Logic Threshold Conversion Circuits

High Speed High Precision Voltage-Mode MAX and MIN Circuits

A Sigma-Delta closed-loop digital microfluxgate magnetometer

Fully Integrated Headphone Detector

Periodically time-varying two-terminals at a steady state, description and identification

Sub-1V Oguey's Current Reference Without Resistance

CMOS Realization of a Quantized-Output Classifier Circuit

Biobjective Hybrid Evolutionary Algorithm Applied to Resonator Filters of Arbitrary Topology

Transition from Sinusoidal to Relaxation Oscillations in Emitter-Coupled Multivibrators

Wireless System for Temperature Measurement in Wheels, based on the ISM Band

Integrated instrumental chain for magnetic pulse measurement in strong static field environment

Global Shutter CMOS Image Sensor With Wide Dynamic Range

The Performance Modeling of Ring Laser Gyro In Inertial Navigation

Contributions to the analysis and design of an ADPLL

Analysis and Design of Antireflection and Frequency Selective Surfaces with Stratified and inhomogeneous media

Design of a SiGe Reconfigurable Power Amplifier for RF Applications: Device and Multi-standard Considerations

Differential Cross-Coupled CMOS VCOs with Resistive and Inductive Tail Biasing

Low power CMOS transmitter for biomedical sensing devices

A novel compact dual-mode bandpass filter using fractal shaped resonators

Fuzzy logic based system for classification of atrial fibrillation cardiac arrhythmias

Design And Implementation Of A Monolithic Programme-Controlled System For Retinal Prosthesis

Reduction of color variability in color image segmentation

High-Resolution 1H NMR Micro spectroscopy using an Implantable Micro-coil

An FPGA-based genetic microarray processing device

CMOS BDJ detector array with charge preamplifiers for sensitive biochemical analysis

Design of Reliable CMOS Phase-Locked Loops

Novel Current Sensing Circuit for IDDQ Testing

Algorithms for Compositions of Arithmetic Transforms and Their Extensions

A Low-Power and Low Silicon Area Testable CMOS LNA Dedicated to 802.15.4 Sensor Network Applications

Tamper Resistivity Analysis for Nano-meter LSI with Process Variations

Synthesis Method for BAW Filters Computation

Reconfiguration of Bulk Acoustic Wave Filters: Application to WLAN 802.11b/g (2.40-2.48 GHz)

Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits

Limits to a Correct Evaluation in RTD-based Ternary Inverters

Tunable photonic crystals using ferroelectric materials

Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators

An Ultra Low Power Successive Approximation ADC with Selectable Resolution in 0.13 μm CMOS Technology

Optimizing Resistances and Capacitances of a Continuous-Time ΣΔ ADC

Pixel-level ADC by small charge quantum counting

Enhanced split-architecture delta-sigma ADC

Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers

ACPR Performance Study for Modified LINC Amplifier

Issues on the Design of a Variable Power LINC Amplifier System in SiGe Operating at 2.4 GHz

Envelope/phase delays correction in an EER radio architecture

Integrated MM-Wave MIMO Antenna with Directional Diversity using MEMS Technology

A Robust Blind Image Watermarking Scheme in the SPIHT-Compressed Bit-Stream

Contribution of Custom Instructions on SoPC for iris recognition application

A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation

Coefficient, Pass and Code-Block Parallel Architecture for FBP Coding in JPEG2000

Design of an Area-Efficient Multiplierless Processing Element For Fast Two Dimensional Image Convolution

Modeling and Design of the CMOS Boot-Strapped Inductor for 5-6 GHz Applications

Integrated RF Devices in Suspended Technology

Wide-Band Frequency-Independent Equivalent Circuit Model for Integrated Spiral Inductors in (Bi)CMOS Technology

Performance of Si-Integrated Wide-Band Single-Ended Switched Capacitor Arrays

GA-SVM Optimization Kernel applied to Analog IC Design Automation

AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow

Impact of charge injection on system-level performance of a discrete-time GSM receiver

A New Active Pixel Design using μc-Si TFT Technology to Improve Brightness Uniformity of Organic Displays

A Parallel-In Serial-Out Multiplier Using Redundant Representation for A Class of Finite Fields

Delay Efficient 32-bit Carry-Skip Adder

Request-skip adders : CMOS standard cell data dependent adders

Delay Optimized Redundant Binary Adders

Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders

Implantable Smart Medical Microsystems: Limits and Challenges

Cryogenic SiGe Hetero-Junction Bipolar Transistors From Standard Technologies For Low Noise FLL

Improved Chopper Stabilized Amplifier for Offset and 1/f Noise Cancellation

Optimum Sizing and Compensation of Two-Stage CMOS Amplifiers Based On a Time-Domain Approach

A 5.2-mW, 2.5-Gb/s Limiting Amplifer for OC-48 SONET Applications

Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification

An Efficient H.264 VLSI Advanced Video Encoder

A VLSI Decoder for the Golden code

A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder

RC-Chain: a Simple Model of Delay with a Ramp Input

Error Detection Code Efficiency for Secure Chips

A Hybrid Method for the Recognition of Acceptor Splice Sites

A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay

Optimized Design of a Digital IQ Demodulator Suitable for Adaptive Predistortion of 3rd Generation Base Station PAs

Design of Sampling-Based Downconversion Stage for Multistandard RF Subsampling Receiver

Shot-Noise Analysis in Circuits with Large Signal Excitations using Harmonic Balance Simulators

Maximum frequency of operation of CMOS Static Frequency dividers: Theory and Design techniques

Programmable Gain Amplifiers based on High-Linearity MOS Current Dividers

Compact, low-power, analogue building blocks derived from MOSFETs translinear loops

Constant gm, rail-to-rail input transconductance stage with output common mode current compensation

New 1.5-V CMOS Current Feedback Operational Amplifier

Simulating the Effects of Process Variations on Capacitive Crosstalk

Power and Failure Analysis of CAM Cells Due to Process Variations

An Embedded Rectifier-Based Built-In-Test Circuit for CMOS RF Circuits

System-Level ESD Protection Design with On-Chip Transient Detection Circuit

A Low-Power Highly Linear CMOS Transconductance Topology

A Low-noise Low-offset Op Amp in 0.35μm CMOS Process

Bandwidth Extension of High-Gain CMOS Stages Using Active Negative Capacitance

A 1.5-V, Constant-Gm, Rail-to-Rail Input Stage Operational Amplifier

A Time-Consistent Video Segmentation Algorithm designed for Real-Time Implementation

Fuzzy classification, image segmentation and shape analysis for Human face detection

Research on An Improved Anisotropic High-pass Filtering Algorithm Based on the Step Angle Searching

Unequal Error Protective and Standard Compatible Multiple Descriptions Coding for Image Communication

Comparison of Three Methods of Eliminating Musical Tones in Speech Denoising Subtractive Techniques

Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS

A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits

Analysis of the intermodulation distortion and nonlinearity of common-base SiGeC HBTs.

A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13μm CMOS

Broadband Modelling of a High Efficiency Rectenna for Batteryless RFID Systems

Analysis and optimization of power line coupling circuit for CENELEC-PLC Modem

Analog Circuits for Symbol-Likelihood Computation

A Simple Method for Transmission with Reduced Crosstalk and Echo

Benefits of prior speech segmentation for best time-frequency visualisation using Renyi's entropy

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism

Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion

Testing QCA Modular Logic

Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement

Ultra-Small RLID Chip Technology

A Compensation Method for Magnitude Response Mismatches in Two-channel Time-interleaved Analog-to-Digital Converters

Analog to digital conversion using a Pulse Width Modulator and an irregular sampling decoder

High-Efficiency Regulated Charge Pump for Non-Volatile Memories

High-Efficiency CMOS Charge Pump

Reduced Complexity Power Minimization Algorithm for DMT Transmission - Application to Layered Multimedia Services over DSL

Improving the Security of the Shi Reversible Data Hiding Algorithm

Teleoperation via Internet with Time-Varying Delay

Improved Transient Frequency Response of IIR Filters with Multiple Frequency Initialization

Output Frequencies of A Class of Nonlinear Systems

ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis

High Performance Timing-Driven Rank Filter

Camera-based Digit Recognition System

A Full-Color QVGA Microdisplay using Light-Emitting-Polymer on CMOS

High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine

A Micro-architecture Simulator for Multimedia Stream Processor

Intra- and Inter-Processors Memory Size Estimation for Multithreaded MPSoC Modeled in Simulink

Trusted computing - A new challenge for embedded systems

Multi-Bank Memory Allocation for Multimedia Application

IP Generation Targeting Multiple Bit-Width Standards

Digital Radio Front-End for High Data Rate Impulse UWB System

UWB LNAs using LC ladder and transformers for input matching networks

FM-UWB: A Low-Complexity Constant Envelope LDR UWB Approach

Effect of RF Front-End Parameters on UWB-OFDM Receiver Performances in Presence of Adjacent Channel Interferers

Two-Dimensional FIR Signal Adapted Filter Banks

A High Performance VLSI FFT Architecture

An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA

Ultra low voltage CMOS gates

SystemC-defined SIMD instructions for high performance SoC architectures

Architecture of an Efficient Area and Flexible Multi-CODEC Processor

Oversampled and Noise-Shaped Pulse-Width Modulator for High-Fidelity Digital Audio Amplifier

Strategies for adaptive nonlinear noise reduction Volterra-Wiener filter structure selection

An 11Gb/s CMOS Demultiplexer Using Redundant Multi-valued Logic

Implementation of Multiplier Block with Reduced Adder Cost

SAD-Based Stereo Matching Circuit for FPGAs

Systematic Lossy Error Protection of Video based on Reduced Spatial Resolution

A Real-time Control System for Home/Office appliances automation, from mobile device through GPRS network

Performance of DSSS against Repeater Jamming

Committee Machine with Over 95% Classification Accuracy for Combustible Gas Identification

Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors

Hybrid method for cereal grain identification using morphological and color features

Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis

Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface

Modeling of Feedback Analog Circuits with VHDL

3 Megapixel Camera Signal Processor for Mobile Camera Applications

An Implementation of Integrable Low Power Techniques for Modern Cell-Based VLSI Designs

Modeling of Operational Amplifier based on VHDL-AMS

Effect of Simultaneous Switching Noise on an Analog Filter

A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler

FPAA Prototyping of ΣΔ Analog Digital Converters

Implementation of a Mixed Signal Chip for Multichannel Audio Equalizer with Sigma-delta A/D Conversion

Accuracy Improvement by Nonlinearity Reduction in Two-Frequency Laser Heterodyne Interferometer

Optimal Dark Current Reduction in Quantum Well 9 μm GaAs/AlGaAs Infrared Photodetectors With Improved Detectivity

Design and Test of a CMOS MLP Analog Neural Network for Fast On-Board Signal Processing

An Analog-Digital Neural Processor for Integrated Sensor Conditioning

Exponential Stability for Cellular Neural Networks with Delay

Using FPGAs to Implement Artificial Neural Networks

A LVDS Serial AER Link

FPGA Implementation of Programmable Pulse Mode Neural Network with on Chip Learning for signature application

Design of a modular and mixed neuromimetic ASIC

A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology

A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback

On the calibration of AD and DA converters based on R/ßR ladder networks

Continuous-Time Complex Bandpass Modulator: Key Component for Highly Digitized Receiver

Scaling Input Signal Swings of Overloaded Integrators in Resonator-based Sigma-Delta Modulators

Secured and Seamless Handoff in Wireless Fourth Generation Systems

Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless Receiver

On the Use of a Performance Indicator for Optimal Pilot Positioning in Multicarrier Systems

Telecommunication synchronisation developpement based on high level virtual prototype

A Low Complexity Simulation Algorithm for TH-UWB MMSE RAKE Receiver in NLOS Channel

A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe:C Technology

A Digital Frequency Shift Keying Demodulator

RF Digital Predistorter for Power Amplifiers of 3G Base Stations

A 20-GHz and 46-GHz, 32x6-bit ROM for DDS Application in InP DHBT Technology

4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS

79 GHz Fully Integrated Fully Differential Si/SiGe HBT Amplifier for Automotive Radar Applications

A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection

A 4mA, 0.25 SiGe, 23GHz BiFET Low Noise Amplifier

A Dual Stage GaAs Amplifier for a K-Band Direct Receiver

Low Power 38-GHz UWB Tunable LNA Design Using SiP Technology

Compact Modeling and Applications of CNTFETs for Analog and Digital Circuit Design

A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors

3D simulation of thin-film bulk acoustic wave resonators (FBAR)

An Improved Isolation W-CDMA Ladder BAW-SMR Filter

Intermediate Frequency Lamb Wave Resonators and Filters for RF Receiver Architectures

Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison

Pre-conditioning Free Footless DCVSL for High-performance Datapaths

orBDDs Direct Mapping for Structured Logic Circuits

Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining

Exact Minimum Logic Factoring via Quantified Boolean Satisfiability

Designing Analog Circuits with Reduced Biasing Power

BiCMOS vs. CMOS Operational Amplifiers for High-Speed Pipelined A/D Converters

Frequency Response Analysis of Latch Utilized in High-Speed Comparator

A Systolic Inversion Architecture Based on Modified Extended Euclidean Algorithm for GF(2K) Fields

Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable system

Applying Low Power Techniques in AES MixColumn/InvMixColumn Transformations

Lock and Unlock: A Data Management Algorithm for A Security-Aware Cache

An offset and gain calibration method for time-interleaved analog to digital converters

Leakage Power Minimization of Nanoscale CMOS Circuits via Non-Critical Path Transistor Sizing

Recursive Least-Squares Lattice Adaptive Algorithm Suitable for Fixed-Point Implementation

Implementation and Synthesis of a Sorting Network

Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RE transmitters

A Study of High-Frequency Bandpass Delta-Sigma Transmitter Architectures

A ΣΔ fractional- N synthesizer for GSM standard specifications

A Programmable Complex FIR Filter with Integrated MEMS Filter for Front-end Charge Sampling Receiver

Direct Form I Active Optical Filters Realized in an Integrated Photonic Architecture

A 100dB dynamic range CMOS image sensor with global shutter

A 1Gb/s 4-Channel Optical Transceiver Chipset for Automotive Wired Networks

High-Performance Pixelwise Readout Integrated Circuits for Microbolometer

Low-power 2.4-GHz RF transceiver for wireless EEG module plug-and-play

A New PhotoFET for Monolithic Active Pixel Sensors Using CMOS Submicronic Technology

A Comparison between Centerlized and Distributed agent-based Evolutionary Target Tracking System

A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC

Investigation of Timing Jitter in NAND and NOR Gates Induced by Power-Supply Noise

Track-and-Latch Comparator Design Using Associations of MOS Transistors and Characterization

A Wide-Range Delay-Locked Loop with a New Lock-Detect Circuit

Power Macromodeling for IP Modules

Acceleration for a compiled Transaction Level Modeling simulation

Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core

Pole optimisation of GOB-Volterra model for non linear MISO system

Address Generation Techniques for Conflict Free Parallel Memory Accessing in FFT Architectures

Cell Ratio Bounds for Reliable SRAM Operation

Leakage Energy Reduction in Banked Content Addressable Memories

Switched Polarity Charge Pump for NOR-type Flash Memories

An RF-ID Receiver Using SAW Filters For Wideband Synchronisation

A Fully Integrated 2.45-GHz Frequency Synthesizer and FSK Modulator

A New Simple UWB Monocycle Pulse Generator

A Low-Power High-Rate Modulator for Ultra-Wideband Transmitters

A Pre-processing Based Real-Time Address Tracer for Embedded Microprocessors

Efficient Post-Processing Module for a Chaos-based Random Bit Generator

Hardware-Software Co-design of a Dynamically Reconfigurable FPGA-based Fuzzy Logic Controller

A Programmable Hardware Cellular Automaton : Example of Data Flow Transformation

A novel architecture for remote interrogation of wireless battery-free capacitive sensors

A new Polysilicon TFT capacitive fingerprint sensor with advanced mismatch compensation

A Hardware Library for Sensors/Actuators Interfaces in Sensor Networks

MAC Protocol for Low-Power Real-Time Wireless Sensing and Actuation

On Stability of Synchronized van der Pol Oscillators

A 900 MHz Multiphase LC Oscillator with Sinusoidal Outputs in SiGe Technology

Detailed Solution Curves and Bifurcation Boundaries of the Forced van der Pol Oscillator

Application of the inductor multiplier

An optimized low voltage and High Frequency CCII based multifunction Filters

A UML-based Environment for System Design Space Exploration

An Efficient FPGA Implementation of Gaussian Mixture Models-Based Classifier Using Distributed Arithmetic

Wave Pipelining using Self Reset Logic

A NAND Flash Memory Controller for SD/MMC Flash Memory Card

An Efficient Hardware Implementation of a Robust and Low-Complexity ADSRC Timing Synchronization Design

A Low Power Sense Amplifier Flip-Flop With Balanced Rise/Fall Delay

Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating Gate Designs

Precharge Node based Variable Forward Body Bias for Low-Energy LSIs

Design of a flexible low-power modem chip for point to point radio link cellular backhaul applications

A Design Methodology for High-Speed Low-Power MCML Frequency Dividers

Low-Power RF Transceiver for IEEE 802.15.4 (ZigBee) Standard Applications

Wide-band 0.9 GHz to 4 GHz Four-Port Receiver

Automated Design of a WCDMA/WLAN Multi-standard Receiver

Optimized AIS/DSC homodyne receiver design

A 3.110.6 GHz CMOS Direct-Conversion Receiver for UWB Applications

Robust Symmetric Multiplication for Programmable Analog VLSI Array Processing

Finding the Number of Clusters in a Dataset Using an Information Theoretic Hierarchical Algorithm

Artificial Neural Network Optimization for FPGA

Simple Analogue VLSI Circuit of a Cortical Neuron

Modelling the XOR/XNOR Boolean Functions Complexity Using Neural Network

Scalable Model for Multi-Standard Phase Locked Loop

Noise and Jitter in CMOS Digitally Controlled Delay Lines

Frequency-Path Modeling for Three-Longitudinal-Mode Interferometer

Area-Driven White Space Distribution for Detailed Floorplan Design

Dynamic Element Matching for Low-power /spl Sigma//spl Delta/Modulator with R-C based internal DAC

2005 12th IEEE International Conference on Electronics, Circuits and Systems

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003

9th International Conference on Electronics, Circuits and Systems

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

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ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)

1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196)

Proceedings of Third International Conference on Electronics, Circuits, and Systems

A VLSI Decoder for the Golden code

Content Provider	IEEE Xplore Digital Library
Author	Cerato, B. Masera, G. Viterbo, E.
Copyright Year	2006
Description	Author affiliation: Politecnico di Torino, Torino (Cerato, B.; Masera, G.; Viterbo, E.)
Abstract	The proposed golden code is an optimal space-time block for 2 times 2 multiple input multiple output (MIMO) system, to be used in wireless transmission to achieve high reliability and throughput. The aim of this work is the design of a VLSI decoder for a MIMO system coded with the golden code. This architecture is based on the sphere decoding algorithm that allows maximum likelihood decoding performance, with polynomial search complexity. The proposed architecture exhibits an inherent flexibility with respect to different modulation schemes (4, 16, 64-QAM), which makes it particularly suitable for adaptive modulation schemes.
Starting Page	549
Ending Page	552
File Size	399444
Page Count	4
File Format	PDF
ISBN	1424403944
DOI	10.1109/ICECS.2006.379847
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-10
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration MIMO Maximum likelihood decoding Transmitting antennas Maximum likelihood detection Wireless LAN Fading Receiving antennas Detectors Throughput
Content Type	Text
Resource Type	Article

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