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Content Provider | IEEE Xplore Digital Library |
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Author | Zheng Peng Xiong Osenbach, J.W. Kok Hua Chua |
Copyright Year | 2006 |
Description | Author affiliation: Agere Syst. Singapore Pte Ltd. (Zheng Peng Xiong; Osenbach, J.W.; Kok Hua Chua) |
Abstract | The study is aimed at uncovering the root cause of brittle failure on large-die FCBGA packages built with electroless Ni/immersion Au (ENIG) plated build-up substrate. The failure was resultant from interfacial cracks between Sn/Ni inter-metallic layer and Ni(P) layer of eutectic Sn/Pb bump joints near die edge. Detailed metallurgical analysis shows the affected substrate exhibits over-etch phenomenon at Ni nodules, which is consistent as black pad effect that the industry has studied. Non-linear finite element analysis conducted on two large-die FCBGA structures with different performances in bump cracking proves the effect of bump array design on stress distribution: Sparse bump array layout and/or large depopulated bump array design would significantly increase the stress at those critical bump joints due to the reduced bump population density. An alternative surface finish "Cu-SOP" finish, bare copper with a coated solder, was also evaluated for its propensity for brittle fracture and compared with ENIG finish that did not contain any evidence of black pad. This was done by applying a mechanical twisting test for assembled flip chips. After the destructive test, 66% ~ 73% bumps per die failed at the bump/substrate interface for the assemblies made on substrates with an ENIG surface finish, all in brittle fracture mode. In contrast, on substrates with Cu-SOP pad finish, almost 100% of the bumps per die broke at die/bump interface, rather than bump/substrate interface. Even on those few bumps broken at bump/substrate interface, the failure mode was found either ductile mode or pad peel-off. This result indicated superior interfacial fracture strength for Cu-SOP surface finish as compared to ENIG surface finish |
Starting Page | 196 |
Ending Page | 202 |
File Size | 1645052 |
Page Count | 7 |
File Format | |
ISBN | 1424406641 |
DOI | 10.1109/EPTC.2006.342715 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2006-12-06 |
Publisher Place | Singapore |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Tin Flip chip Electronics packaging Surface cracks Surface finishing Stress Testing Assembly Gold Metals industry |
Content Type | Text |
Resource Type | Article |
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