NDLI: Substrate designs to improve die crack damage in CSP

Content Provider	IEEE Xplore Digital Library
Author	Kao, N. Wang, Y.P. Chou, S. Tsai, Y.L. Her, T.D.
Copyright Year	2001
Description	Author affiliation: R&D Div., Siliconware Precision Industries Co. Ltd., Taichung, Taiwan (Kao, N.)
Abstract	For development and design of high performance ICs, more and more functions are required to be contained in a chip scale package (CSP) for applications that require low profiles and small footprints. With thinner package profile requirements, thinner substrates are necessary. More reliability issues arise with thinner substrates to provide mechanical support. The different kinds of substrate design layout induce different stress distributions which affect the IC directly during various assembly processes. These propagating effects may finally cause die crack damage. Therefore, proper substrate layout design does not only achieve thermal and electrical functional requirements, but also prevents critical mechanical problems. The purpose of this paper is to investigate mechanical effects on the IC of different substrate design patterns. Furthermore, to improve the influence of the optimal substrate layout, a dummy copper layer is used within the substrate. For comparison and confirmation of these phenomena, both numerical analysis (FEA) and experiment measurements were employed. CSPs were used as the test vehicle. Effects of dummy patterns were observed during the assembly process. There is no chip damage observed with modified substrate design. For further investigation of other possible factors, substrate thickness was varied in the FEA model. It was proved that the design effect is insignificant with thicker substrates. A similar result was observed with parameters of chip thickness, and Moire interferometry was engaged to verify FEA models.
Sponsorship	Korea Sci. & Eng. Found.
Starting Page	444
Ending Page	449
File Size	592258
Page Count	6
File Format	PDF
ISBN	0780371577
DOI	10.1109/EMAP.2001.984025
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-19
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chip scale packaging Assembly Thermal stresses Integrated circuit layout Copper Numerical analysis Semiconductor device measurement Testing Vehicles Interferometry
Content Type	Text
Resource Type	Article

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