NDLI: Development of molding compounds for BGA

Content Provider	IEEE Xplore Digital Library
Author	Oota, K. Shigeno, K.
Copyright Year	1995
Description	Author affiliation: Electron. Device Mater. Res. Lab., Sumitomo Bakelite Co. Ltd., Utsunomiya, Japan (Oota, K.; Shigeno, K.)
Abstract	Recently, semiconductor packages have become thinner and smaller like TSOP and TQFP in accordance with the trend from insert type to surface mount devices. On the other hand, pin counts have become more and more due to higher integration and functions of semiconductor devices, and in this background, BGA is now newly being put to practical use instead of QFP as it can be mounted on PWBs easily. The difference of BGA from conventional package designs like QFP is one-side molding, and specific properties are required for molding compounds for BGA in comparison to requirements for conventional packages. Therefore, we started development of molding compounds for BGA for satisfying specific requirements. At first we analyzed stress by FEM and investigated the relation to package warpage. The warpage occurred in the stress concentration area and CTE and Tg were found to influence the warpage especially. We made molding compound samples of various CTE, Tg, and so on for this study and could confirm correlations with the analysis result. This result gave us a direction of molding compound development for warpage prevention. Next, as a substrate is used for BGA instead of a metal leadframe for conventional packages, we checked adhesion to the substrate and found additives for better adhesion. From the above results, we have developed new molding compounds for BGA, which have small warpage and good adhesion to the substrate.
Starting Page	78
Ending Page	85
File Size	644407
Page Count	8
File Format	PDF
ISBN	0780327365
DOI	10.1109/ECTC.1995.514365
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Pins Semiconductor device packaging Substrates Adhesives Packaging machines Inductance Stress Printed circuits Wire
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Adhesion Promotion Technology for Semi-Additive Process

Low-Cost Vacuum Molding Process for BGA Using a Large Area Substrate

Reliability study of ceramic substrate in a SIP type package

Welding Research

Development of Sn-Pb-Bi solder materials for fine pitch package

SSO noise electrical performance limitations for PQFP packages

Programmability concept of PGA package power and ground pins applicable to different gate array chip designs

Chip-package codesign for high-frequency circuits and systems

Controlled collapse chip connection (C4)-an enabling technology

Development of molding compounds for BGA

Similar Documents

Adhesion Promotion Technology for Semi-Additive Process

Low-Cost Vacuum Molding Process for BGA Using a Large Area Substrate

Reliability study of ceramic substrate in a SIP type package

Welding Research

Development of Sn-Pb-Bi solder materials for fine pitch package

SSO noise electrical performance limitations for PQFP packages

Programmability concept of PGA package power and ground pins applicable to different gate array chip designs

Chip-package codesign for high-frequency circuits and systems

Controlled collapse chip connection (C4)-an enabling technology

Development of molding compounds for BGA