NDLI: Silver Mentor and ASE

Please wait, while we are loading the content...

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)

2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems

2013 IEEE 22nd Conference on Electrical Performance of Electronic Packaging and Systems

2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems

Welcome message

Table of contents

EPEPS-2011 Technical Program Committee (TPC)

All sponsor page

Silver sponsor Apache

Silver Agilent and 3 DIC-RC

Silver Mentor and ASE

Silver Nimbic and TI

Power integrity in high-speed designs (M-IV)

Plane bounce in high-speed single-ended signaling I/O interfaces

Practical aspects of modeling apertures for signal and power integrity co-simulation

Verification of novel technology for power integrity on 16-channel 3Gbps circuit boards

Design strategies for processor, chip/package co-design (M-VI)

Deriving voltage tolerance specification for processor circuit design

Early stage chip/package/board co-design techniques for system-on-chip

Novel RF and chip-to-chip interconnects (M-VII)

High-density silicon carrier transmission line design for chip-to-chip interconnects

Wireless RF data communications using 60 GHz antennas in Multi-Core systems

Electrical performance of vertical natural capacitor for RF system-on-chip in 32-nm technology

Macromodeling and circuit analysis (M-IX)

Alternative SPICE implementation of circuit uncertainties based on orthogonal polynomials

Sequential sampling strategy for the modeling of parameterized microwave and RF components

Fast rational function fitting of broadband multi-port responses via repeated random sampling

A compression strategy for rational macromodeling of large interconnect structures

Jitter modeling and analysis (M-XI)

Spectral relations of supply noise and jitter with regular and feed forward clocking schemes

Extraction of jitter parameters from BER measurements

Measurements methodologies for signal integrity (T-II)

A methodology for RF modeling of packages using IC known-loads

Electrical performance of high speed signaling in coupled microstrip lines

Optimized coplanar waveguides in membrane technology for wideband on-wafer calibrations

New interconnect evaluation metric for high-speed IO

Emerging technologies: 3D ICs & clock distribution (T-V)

Distributed multi TSV 3D clock distribution network in TSV-based 3D IC

Adaptive clock distribution for 3D integrated circuits

High-speed performance of Silicon Bridge die-to-die interconnects

TSV modeling (T-VI)

Through-silicon via (TSV) depletion effect

Impact of Through-Silicon-Via capacitance on high frequency supply noise in 3D-stacks

Modeling and simulation of MTLs (T-VIII)

Waveform relaxation and overlapping partitioning techniques for tightly coupled interconnects

Fast iterative simulation of high-speed channels via frequency-dependent over-relaxation

An analytical resistive loss model for multiconductor transmission lines and the proof of its passivity

Advanced simulation methodologies for SI analysis (T-IX)

Latency insertion method (LIM) for CMOS circuit simulations with multi-rate considerations

Simulations of pulse signals with X-parameters

High-speed links design (T-XI)

Design and analysis of 12.8 Gb/s single-ended signaling for memory interface

Embedded equalization for ADC-based serial I/O receivers

System design considerations for a 5Gb/s source-synchronous link with common-mode clocking

Interconnect channel characteristics favoring double-edge pulsewidth modulation

EM methods for variability analysis (W-III)

Macromodeling based variability analysis of an inverted embedded microstrip line

Interconnect transient simulation in the presence of layout and routing uncertainty

Random rough surface effects in interconnects studied by small perturbation theory in waveguide model

Parallel EM computing for packages (W-V)

Towards system-level electromagnetic field simulation on computing clouds

Fast full-wave modeling of passive structures with graphic processors

Advances in EM algorithms (W-VI)

Mixed integral-differential skin-effect models for PEEC electromagnetic solver

Full-wave PEEC time domain solver based on leapfrog scheme

An explicit and unconditionally stable time-domain finite-element method of linear complexity for electromagnetics-based simulation of 3-D global interconnect network

Accuracy-improved through-silicon-via model using conformal mapping technique

Poster session (M-XII)

Modeling of ISI in high speed serial I/Os terminated with discontinuities

SI-aware layout and equalizer design to enhance performance of high-speed links in blade servers

Switching regulator noise coupled onto high speed differential links

3D via modeling simplification on multilayer mid-planes

Common-mode noise reduction schemes for differential serpentine delay microstrip line in high-speed digital circuits

Design of a 12Gb/s transceiver for high-density links with discontinuities using modal signaling

A de-embedding method for extracting S-parameters of vertical interconnect in advanced packaging

Passive model-order reduction of RLC circuits with embedded time-delay descriptor systems

A new method to estimate phases of sinusoidal jitter to evaluate high-speed links

Electrical performance of inkjet printed flexible cable for ECG monitoring

Decoupling capacitor stacked chip (DCSC) in TSV-based 3D-ICs

A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC

High-frequency through-silicon Via (TSV) failure analysis

Temperature-dependent through-silicon via (TSV) model and noise coupling

Signal-integrity improvement based on the segmental-transmission-line

Waveform relaxation based analysis of noise propagation in power distribution networks

Reduced circuit modeling of mother board and package for a system power delivery analysis

Application of the latency insertion method to electro-thermal circuit analysis

Analysis and approach of TSV-based hierarchical power distribution networks for estimating $1^{st}-Droop$ and resonant noise in 3DIC

Capacitance calculation for a shared-antipad via structure using an integral equation method based on partial capacitance

Three finite-element time-domain-based numerical algorithms for high-frequency broadband PCB simulations

CAD model reconstruction of solder balls for the computationally efficient electromagnetic field simulation

Optimal decoupling capacitors design for suppressing edge radiation of power/ground planes

Design of power delivery networks using power transmission lines and pseudo-balanced signaling for multiple I/Os

Bended differential transmission line using short-circuited coupled line for common-mode noise suppression

A comparison of two latency insertion methods in dependent sources applications

Twelve pseudo-differential transmission schemes

Compact stepped-impedance resonator transformer

Efficient spectral domain analysis of multilayered shielded microstrip using two super convergent series

19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems

2008 IEEE-EPEP Electrical Performance of Electronic Packaging

2007 IEEE Electrical Performance of Electronic Packaging

2006 IEEE Electrical Performane of Electronic Packaging

IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005.

Electrical Performance of Electronic Packaging - 2004

Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710)

Electrical Performance of Electronic Packaging,

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)

IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.00TH8524)

IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)

IEEE 7th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.98TH8370)

Electrical Performance of Electronic Packaging

Proceedings of Electrical Performance of Electronic Packaging

Proceedings of 1994 IEEE Electrical Performance of Electronic Packaging

Proceedings of IEEE Electrical Performance of Electronic Packaging

[1992 Proceedings] Electrical Performance of Electronic Packaging

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in