NDLI: Receiver Design and Performance Evaluation for MIMO Integrated GSM Systems

Content Provider	IEEE Xplore Digital Library
Author	Yong Jin Daniel Kim Bajcsy, J.
Copyright Year	2007
Description	Author affiliation: McGill Univ., Montreal (Yong Jin Daniel Kim; Bajcsy, J.)
Abstract	We investigate feasibility of multiple-input-multiple-output (MIMO) technology integration with the existing GSM transceiver architecture. System level performance gains are explored for the full-rate GSM data traffic channel combined with multiple-antenna uplink transmission with $n_{tau}$ transmit and nR receive antennas. We consider the typical urban environment with Rayleigh fading, when the channel state information is available at the receiver only. The designed receiver adopts a linearly complex MIMO signal detector based on the space matched filtering principle [8] for the GMSK modulation used in the GSM standard. The detector is further integrated with two iterative equalizers that use either iterative turbo equalization or probabilistic data association to provide additional performance gains. Simulated bit-error rate performance results for various antenna configurations illustrate that the MIMO integration can provide dramatic performance gains when compared to the traditional single-antenna GSM system. A potential application for this technology is high rate uploading of multimedia contents generated by mobile users.
Starting Page	316
Ending Page	319
File Size	264893
Page Count	4
File Format	PDF
ISBN	1424410207
ISSN	08407789
DOI	10.1109/CCECE.2007.85
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MIMO GSM Performance gain Detectors Transceivers Receiving antennas Rayleigh channels Channel state information Signal design Signal detection
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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