NDLI: Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks

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2015 Euromicro Conference on Digital System Design

2014 17th Euromicro Conference on Digital System Design

2013 Euromicro Conference on Digital System Design

2012 15th Euromicro Conference on Digital System Design

2011 14th Euromicro Conference on Digital System Design

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

Table of Contents

Conference Information

A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC

An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs

An Effective Replacement Strategy of Cache Memory for an SMT Processor

An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload

A Priority-Based Budget Scheduler with Conservative Dataflow Model

Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation

Distributed Collaborative Design of a Mixed-Signal IP Component

A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling

Improving Latency of Quantum Circuits by Gate Exchanging

Run-Time Reconfigurable Array Using Magnetic RAM

Robustness Check for Multiple Faults Using Formal Techniques

Instruction Precomputation for Fault Detection

Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic

High Availability Fault Tolerant Architectures Implemented into FPGAs

Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip

Exploration of Slot Allocation for On-Chip TDM Virtual Circuits

Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms

Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks

Power Management Aware Low Leakage Behavioural Synthesis

Variation-tolerant Design Using Residue Number System

Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis

Combined SD-RNS Constant Multiplication

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs

Model-Driven Design of Embedded Multimedia Applications on SoCs

GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids

Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors

Reliability Estimation Process

Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems

Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems

High Performance Image Processing on a Massively Parallel Processor Array

Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment

Low Power Encoding in NoCs Based on Coupling Transition Avoidance

Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources

Storage Architecture for an On-chip Multi-core Processor

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs

A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC

Streaming Reduction Circuit

Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation

Pulse Generation for On-chip Data Transmission

High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output

Performance-Effective Compaction of Standard-Cell Libraries for Digital Design

On the Risk of Fault Coupling over the Chip Substrate

Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints

A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems

Reliable Railway Station System Based on Regular Structure Implemented in FPGA

Dependable Controller Design Using Polymorphic Counters

Internet-Router Buffered Crossbars Based on Networks on Chip

Network-on-Chip Architecture Exploration Framework

Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip

Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study

A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning

Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors

Compilation Technique for Loop Overhead Minimization

Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip

Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques

Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator

An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application

Deductive Fault Simulation for Asynchronous Sequential Circuits

ARROW - A Generic Hardware Fault Injection Tool for NoCs

A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction

Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation

High Reliable Remote Terminal Unit for Space Applications

SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform

Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism

Iterative Algorithm for Compound Instruction Selection with Register Coalescing

CPLD-oriented Synthesis of Finite State Machines

Architecture-Driven Synthesis of Reconfigurable Cells

An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication

Composable Resource Sharing Based on Latency-Rate Servers

A MPSoC Prototyping Platform for Flexible Radio Applications

Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation

Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm

High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic

Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks

The Case for a Balanced Decomposition Process

Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization

Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder

Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture

Survey of Test Data Compression Technique Emphasizing Code Based Schemes

A Concept for Logic Self Repair

A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor

An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions

An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures

Energy and Performance Model of a SPARC Leon3 Processor

Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers

FPGA Accelerator for RNA Secondary Structure Prediction

An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm

xMAML: A Modeling Language for Dynamically Reconfigurable Architectures

A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation

Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution

GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations

A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video

Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models

Design of a Highly Dependable Beamforming Chip

One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

Synthesizing Reversible Circuits for Irreversible Functions

A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms

Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables

Logic Minimization and Testability of 2SPP-P-Circuits

FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash

Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology

Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization

The Parallel Sieve Method for a Virus Scanning Engine

Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm

Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing

An FPGA-Based Embedded System for a Sailing Robot

Ad-hoc WSN in Biological Research

Low Power Free Space Optical Communication in Wireless Sensor Networks

A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes

Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

9th EUROMICRO Conference on Digital System Design (DSD'06)

8th Euromicro Conference on Digital System Design (DSD'05)

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

Euromicro Symposium on Digital System Design, 2003. Proceedings.

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

Proceedings Euromicro Symposium on Digital Systems Design

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