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Content Provider | IEEE Xplore Digital Library |
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Author | Kluter, T. Brisk, P. Ienne, P. Charbon, E. |
Copyright Year | 2009 |
Description | Author affiliation: Sch. of Comput. & Commun. Sci., Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland (Kluter, T.; Brisk, P.; Ienne, P.) |
Abstract | This paper introduces way stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific instruction set extensions (ISEs). Way stealing provides more bandwidth to the ISE-logic than the register file alone and does not require expensive coherence protocols, as it does not add memory elements to the processor. When enhanced with way stealing, ISE identification flows detect more opportunities for acceleration than prior methods; consequently, way stealing can accelerate applications to up to 3.7times, whilst reducing the memory sub-system energy consumption by up to 67%, despite data-cache related restrictions. |
Starting Page | 31 |
Ending Page | 36 |
File Size | 349869 |
Page Count | 6 |
File Format | |
ISBN | 9781605584973 |
ISSN | 0738100X |
DOI | 10.1145/1629911.1629923 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-07-26 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Association for Computing Machinery, Inc. (ACM) |
Subject Keyword | Bandwidth Protocols Permission Acceleration Costs Computer aided instruction Data engineering Circuits and systems Registers Energy consumption Automatic Identification Application-Specific Processors Instruction Set Extensions Way Stealing Memory Coherence |
Content Type | Text |
Resource Type | Article |
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